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author | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
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committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 23:42:26 +0000 |
commit | d27c08c2898d1d74765a7799628d1c18369fd671 (patch) | |
tree | 7ac357d2b44d833c6efe70d1e691c6611c521e8d /src/mainboard/asi/mb_5blmp/Config.lb | |
parent | 547d48ab01049a634dccb16d1847524d5ba93e33 (diff) | |
download | coreboot-d27c08c2898d1d74765a7799628d1c18369fd671.tar.xz |
Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asi/mb_5blmp/Config.lb')
-rw-r--r-- | src/mainboard/asi/mb_5blmp/Config.lb | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb index 65e2fd4c0f..93ac8e6fb6 100644 --- a/src/mainboard/asi/mb_5blmp/Config.lb +++ b/src/mainboard/asi/mb_5blmp/Config.lb @@ -135,11 +135,6 @@ chip northbridge/amd/gx1 # Northbridge device pci 12.2 on end # IDE device pci 12.3 on end # Audio device pci 12.4 on end # VGA (onboard) - # device pci 12.4 on # VGA (onboard) - # chip drivers/pci/onboard - # device pci 12.4 on end - # end - # end device pci 13.0 on end # USB register "ide0_enable" = "1" register "ide1_enable" = "1" |