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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-22 15:57:57 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-22 15:57:57 +0000 |
| commit | 0d5a6accc84530d44f35ba4f3a74b370a1f88f86 (patch) | |
| tree | 13267fee11e95bd5081a47995efc0afe567a9ee2 /src/mainboard/asi | |
| parent | 7411eabcdb544205316dfa90e7e708b4b0495074 (diff) | |
| download | coreboot-0d5a6accc84530d44f35ba4f3a74b370a1f88f86.tar.xz | |
Drop per-board ram_check() calls for now.
Every board had a slightly different invokation, very often commented out
anyway. We could either decide that this is only to be used by developers
during bringup (and thus added manually to romstage.c and removed before
the board gets committed). This method seems to be preferred from what I
have heard on IRC / mailing list in the past.
Or, we add the ram_check() somewhere globally and allow the user to enable
it via menuconfig (possibly only if EXPERT is selected).
Either way, the current method of spreading the calls all over the place is
not really the way to go.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asi')
| -rw-r--r-- | src/mainboard/asi/mb_5blgp/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/asi/mb_5blmp/romstage.c | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 3b7b199f49..3d3367aa85 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -24,7 +24,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c" @@ -40,5 +39,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index 118ded48a3..f79c2437b9 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ static void main(unsigned long bist) report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 0x4000); */ } |