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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-28 11:50:10 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-27 10:18:28 +0200 |
commit | fb2f667da2091ce2194274f95c2d5db024d46e63 (patch) | |
tree | 5c9c72faf4d1279a5c6b64ca2ae8a1a879ac84aa /src/mainboard/asrock/939a785gmh/romstage.c | |
parent | c0f7a1b7d12062595f01442989e4eac2869e5b7a (diff) | |
download | coreboot-fb2f667da2091ce2194274f95c2d5db024d46e63.tar.xz |
nb/amd/amdk8: Link raminit_f.c
For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/939a785gmh/romstage.c')
-rw-r--r-- | src/mainboard/asrock/939a785gmh/romstage.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 0894af9e53..1894fdefb9 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -34,7 +34,6 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -42,10 +41,10 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } |