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| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/mainboard/asrock/939a785gmh | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
| download | coreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/939a785gmh')
| -rw-r--r-- | src/mainboard/asrock/939a785gmh/mainboard.c | 5 | ||||
| -rw-r--r-- | src/mainboard/asrock/939a785gmh/romstage.c | 7 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 1cf1731ce1..945a19f040 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -25,11 +25,10 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <southbridge/amd/sb700/sb700.h> +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" #include "chip.h" -#define SMBUS_IO_BASE 0x6000 - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index b0ae24794f..bd45c166af 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -45,7 +45,8 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/early_setup.c" +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -56,7 +57,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(u32 device, u32 address) { - return smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } #include "northbridge/amd/amdk8/amdk8.h" @@ -101,7 +102,7 @@ static void sio_init(void) pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */ pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */ - /* GPIO30 - unknown output, set to 0 + /* GPIO30 - unknown output, set to 0 GPI31 - unknown input NC? GPI32 - unknown input NC? GPIO33 - unknown output, set to 0. |