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authorPatrick Georgi <patrick@georgi-clan.de>2012-02-16 20:44:20 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-02-17 19:04:31 +0100
commit472efa604158c193bdcd8f357ca52c41eca53ca5 (patch)
treeb44dbe7045988d316f03a807ef34fc360e2ca31a /src/mainboard/asrock/939a785gmh
parentd13e4167a903c1bd69c9ed708987f016dff13d1d (diff)
downloadcoreboot-472efa604158c193bdcd8f357ca52c41eca53ca5.tar.xz
Remove whitespace.
Fix issues reported by new lint test. Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/646 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/939a785gmh')
-rw-r--r--src/mainboard/asrock/939a785gmh/acpi/routing.asl8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
index fa3760e045..fd02eac46b 100644
--- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl
+++ b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
@@ -32,12 +32,12 @@ Scope(\_SB) {
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-
+
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
-
+
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */
@@ -83,7 +83,7 @@ Scope(\_SB) {
Package(){0x0009FFFF, 1, 0, 18 },
Package(){0x0009FFFF, 2, 0, 19 },
Package(){0x0009FFFF, 3, 0, 10 },
-
+
/* Bus 0, Dev A - PCIe internal ethernet */
Package(){0x000AFFFF, 0, 0, 18 },
Package(){0x000AFFFF, 1, 0, 19 },
@@ -146,7 +146,7 @@ Scope(\_SB) {
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
-
+
Name(PS9, Package(){
/* PCIe slot - Hooked to PCIe x1 */
Package(){0x0000FFFF, 0, INTD, 0 },