diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-23 19:12:38 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-10-19 11:23:53 +0000 |
| commit | c700829cd3657f1840be581760ca0a2f13226238 (patch) | |
| tree | 8c6e045281125d20fb0d2b5fa5d861673c81fa32 /src/mainboard/asrock/e350m1/OemCustomize.c | |
| parent | 57760e3cdf19b1339f936bd89f082dc2701397ba (diff) | |
| download | coreboot-c700829cd3657f1840be581760ca0a2f13226238.tar.xz | |
AGESA f14: Drop PlatformGnbPcieComplex.h
These were OEM configurations hidden inside a header file, notation
was already dropped for f15tb and f16kb.
Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/asrock/e350m1/OemCustomize.c')
| -rw-r--r-- | src/mainboard/asrock/e350m1/OemCustomize.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/asrock/e350m1/OemCustomize.c b/src/mainboard/asrock/e350m1/OemCustomize.c index 2ce42e029a..bf928d252d 100644 --- a/src/mainboard/asrock/e350m1/OemCustomize.c +++ b/src/mainboard/asrock/e350m1/OemCustomize.c @@ -15,7 +15,6 @@ #include "AGESA.h" #include <PlatformMemoryConfiguration.h> -#include "PlatformGnbPcieComplex.h" #include <northbridge/amd/agesa/state_machine.h> @@ -24,13 +23,13 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) } }; |