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author | Jens Rottmann <JRottmann@LiPPERTembedded.de> | 2013-03-21 22:21:28 +0100 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-22 01:06:12 +0100 |
commit | db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3 (patch) | |
tree | 643d47e1f168190469f269c9ecf4621b745e3885 /src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h | |
parent | 3db86ccfd7caaec5a1c494dfe3bfe9b092837f65 (diff) | |
download | coreboot-db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3.tar.xz |
Asrock E350M1: Use SPD read code from F14 wrapper
Changes:
- Get rid of the E350M1 mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2497/
AMD f14: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
- Add the ASF init that used to be in the SPD read code into
mainboard_enable()
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
Change-Id: I08c2aebc62facc14f94400ee1ad188901ba73f19
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2875
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h')
0 files changed, 0 insertions, 0 deletions