summaryrefslogtreecommitdiff
path: root/src/mainboard/asrock/e350m1/devicetree.cb
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2014-07-19 00:21:43 +0200
committerNico Huber <nico.h@gmx.de>2014-10-30 11:41:26 +0100
commitc1869666f0904fe78c72265b44b46d1fc9f75a59 (patch)
tree784646612633f3cf8896fa423e91af3116990507 /src/mainboard/asrock/e350m1/devicetree.cb
parent16407abdddb13d74f2eb1c0ac6dc82b31dc6ea21 (diff)
downloadcoreboot-c1869666f0904fe78c72265b44b46d1fc9f75a59.tar.xz
mainboards/asrock/e350m1: Use driver for Nuvoton NCT5572D superio chip
On the ASRock E350M1 a Nuvoton NCT5572D is used as SuperIO-chip. The coreboot port to this board however used the driver of the Winbond W83627HF SuperIO, which is compatible enough to get most stuff working, but which clears bit 6 in register 0x2B. This switches the function of pin 38 of the NCT5572D from RSTOUT1# output to GP36. The PERST# pin of the ethernet chip and the unpopulated miniPCIe slot are connected to this pin, so they didn't get reset during a reboot. Using the newly added driver for the Nuvoton NCT5572D fixes this problem. There is also a trace from the pin 37 of the SuperIO, which can be configured as RSTOUT2#, to pin 82 of the USB3-chip with unknown function. As with the wrong driver, PS/2 keyboard and mouse do work in SeaBIOS and GRUB but not in Linux. Change-Id: I4bc78406afd3b0e10a1b04b561147e0ed94cc494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/6266 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asrock/e350m1/devicetree.cb')
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb36
1 files changed, 17 insertions, 19 deletions
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index e2096c07d4..0690664906 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -54,22 +54,15 @@ chip northbridge/amd/agesa/family14/root_complex
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on # LPC 0x439d
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
+ device pci 14.3 on # LPC
+ chip superio/nuvoton/nct5572d
+ device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
+ device pnp 2e.1 off end # LPT1; same as FDC
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
- device pnp 2e.3 off # Com2
+ device pnp 2e.3 off # IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
@@ -81,19 +74,24 @@ chip northbridge/amd/agesa/family14/root_complex
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
+ irq 0x70 = 0
end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
+ device pnp 2e.7 off end # GIPO689
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.9 off end # GPIO235
device pnp 2e.a on end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
+ io 0x62 = 0x0000 # SB-TSI currently not implemented
irq 0x70 = 5
end
+ device pnp 2e.c off end # PECI
+ device pnp 2e.d off end # SUSLED
+ device pnp 2e.e off # CIRWKUP
+ io 0x60 = 0x0000
+ irq 0x70 = 0
+ end
+ device pnp 2e.f off end # GPIO_PP_OD
end
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}