AGESA fam14 boards: Clean up devicetree

Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30733
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 117 insertions, 117 deletions

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index e8b3ea5b95..e374c417ba 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -14,129 +14,128 @@
 #
 chip northbridge/amd/agesa/family14/root_complex
 	device cpu_cluster 0 on
-			chip cpu/amd/agesa/family14
-				device lapic 0 on end
-			end
+		chip cpu/amd/agesa/family14
+			device lapic 0 on end
+		end
 	end
 	device domain 0 on
 		subsystemid 0x1022 0x1510 inherit
-			chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#				device pci 18.0 on #  northbridge
-				chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-					device pci 0.0 on end # Root Complex
-					device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+		chip northbridge/amd/agesa/family14
+			device pci 0.0 on end # Root Complex
+			device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
 
-					device pci 1.1 on end # Internal HDMI Audio
-					device pci 4.0 on end # PCIE P2P bridge 0x9604
-					device pci 5.0 off end # PCIE P2P bridge 0x9605
-					device pci 6.0 off end # PCIE P2P bridge 0x9606
-					device pci 7.0 off end # PCIE P2P bridge 0x9607
-					device pci 8.0 off end # NB/SB Link P2P bridge
-				end # agesa northbridge
+			device pci 1.1 on end # Internal HDMI Audio
+			device pci 4.0 on end # PCIE P2P bridge 0x9604
+			device pci 5.0 off end # PCIE P2P bridge 0x9605
+			device pci 6.0 off end # PCIE P2P bridge 0x9606
+			device pci 7.0 off end # PCIE P2P bridge 0x9607
+			device pci 8.0 off end # NB/SB Link P2P bridge
+		end # agesa northbridge
 
-				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB
-					device pci 12.2 on end # USB
-					device pci 13.0 on end # USB
-					device pci 13.2 on end # USB
-					device pci 14.0 on # SM
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE	0x439c
-					device pci 14.2 on end # HDA	0x4383
-					device pci 14.3 on # LPC
-						chip superio/nuvoton/nct5572d
-							device pnp 2e.0 off end #  FDC; not externally available on the NCT5572D, but on the die
-							device pnp 2e.1 off end #  LPT1; same as FDC
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  IR
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-								irq 0x70 = 0
-							end
-							device pnp 2e.107 off end #  GPIO6
-							device pnp 2e.207 off end #  GPIO7
-							device pnp 2e.307 on #  GPIO8
-								irq 0x23 = 0x28
-								irq 0xe4 = 0xbf
-								irq 0xed = 0x27
-							end
-							device pnp 2e.407 off end #  GPIO9
-							device pnp 2e.8 off end #  WDT
-							device pnp 2e.009 on #  GPIO2
-								irq 0x2a = 0x42
-								irq 0xe0 = 0xe3
-							end
-							device pnp 2e.109 off end #  GPIO3
-							device pnp 2e.209 off end #  GPIO4
-							device pnp 2e.309 off end #  GPIO5
-							device pnp 2e.a on #  ACPI
-								irq 0xe7 = 0x10
-							end
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								io 0x62 = 0x0000 #  SB-TSI currently not implemented
-								irq 0x70 = 5
-							end
-							device pnp 2e.c off end #  PECI
-							device pnp 2e.d on #  SUSLED
-								irq 0xec = 0x90
-							end
-							device pnp 2e.e off #  CIRWKUP
-								io 0x60 = 0x0000
-								irq 0x70 = 0
-							end
-							device pnp 2e.f off end #  GPIO_PP_OD
-						end
-					end #LPC
-					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-					device pci 14.5 on end # USB 2
-					device pci 15.0 on  end # PCIe PortA
-					device pci 15.1 on  end # PCIe PortB: NIC
-					device pci 15.2 on  end # PCIe PortC: USB3
-					device pci 15.3 off end # PCIe PortD
-					device pci 16.0 off end # OHCI USB3
-					device pci 16.2 off end # EHCI USB3
+		chip southbridge/amd/cimx/sb800
+			device pci 11.0 on end # SATA
+			device pci 12.0 on end # USB
+			device pci 12.2 on end # USB
+			device pci 13.0 on end # USB
+			device pci 13.2 on end # USB
+			device pci 14.0 on # SM
+				chip drivers/generic/generic #dimm 0-0-0
+					device i2c 50 on end
+				end
+				chip drivers/generic/generic #dimm 0-0-1
+					device i2c 51 on end
+				end
+			end # SM
+			device pci 14.1 on end # IDE	0x439c
+			device pci 14.2 on end # HDA	0x4383
+			device pci 14.3 on # LPC
+				chip superio/nuvoton/nct5572d
+					device pnp 2e.0 off end #  FDC; not externally available on the NCT5572D, but on the die
+					device pnp 2e.1 off end #  LPT1; same as FDC
+					device pnp 2e.2 on #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off #  IR
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on #  Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off #  CIR
+						io 0x60 = 0x100
+						irq 0x70 = 0
+					end
+					device pnp 2e.107 off end #  GPIO6
+					device pnp 2e.207 off end #  GPIO7
+					device pnp 2e.307 on #  GPIO8
+						irq 0x23 = 0x28
+						irq 0xe4 = 0xbf
+						irq 0xed = 0x27
+					end
+					device pnp 2e.407 off end #  GPIO9
+					device pnp 2e.8 off end #  WDT
+					device pnp 2e.009 on #  GPIO2
+						irq 0x2a = 0x42
+						irq 0xe0 = 0xe3
+					end
+					device pnp 2e.109 off end #  GPIO3
+					device pnp 2e.209 off end #  GPIO4
+					device pnp 2e.309 off end #  GPIO5
+					device pnp 2e.a on #  ACPI
+						irq 0xe7 = 0x10
+					end
+					device pnp 2e.b on #  HW Monitor
+						io 0x60 = 0x290
+						io 0x62 = 0x0000 #  SB-TSI currently not implemented
+						irq 0x70 = 5
+					end
+					device pnp 2e.c off end #  PECI
+					device pnp 2e.d on #  SUSLED
+						irq 0xec = 0x90
+					end
+					device pnp 2e.e off #  CIRWKUP
+						io 0x60 = 0x0000
+						irq 0x70 = 0
+					end
+					device pnp 2e.f off end #  GPIO_PP_OD
+				end
+			end #LPC
+			device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+			device pci 14.5 on end # USB 2
+			device pci 15.0 on  end # PCIe PortA
+			device pci 15.1 on  end # PCIe PortB: NIC
+			device pci 15.2 on  end # PCIe PortC: USB3
+			device pci 15.3 off end # PCIe PortD
+			device pci 16.0 off end # OHCI USB3
+			device pci 16.2 off end # EHCI USB3
 
-					# gpp_configuration options
-					#0000: PortA lanes[3:0]
-					#0001: N/A
-					#0010: PortA lanes[1:0], PortB lanes[3:2]
-					#0011: PortA lanes[1:0], PortB lane2, PortC lane3
-					#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
-					register "gpp_configuration" = "4"
+			# gpp_configuration options
+			#0000: PortA lanes[3:0]
+			#0001: N/A
+			#0010: PortA lanes[1:0], PortB lanes[3:2]
+			#0011: PortA lanes[1:0], PortB lane2, PortC lane3
+			#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
+			register "gpp_configuration" = "4"
 
-					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/cimx/sb800
-#				end #  device pci 18.0
-#
-# These seem unnecessary
-				device pci 18.0 on end
-				device pci 18.1 on end
-				device pci 18.2 on end
-				device pci 18.3 on end
-				device pci 18.4 on end
-				device pci 18.5 on end
-				device pci 18.6 on end
-				device pci 18.7 on end
+			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+		end	#southbridge/amd/cimx/sb800
+
+		chip northbridge/amd/agesa/family14
+
+			# These seem unnecessary
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
 
 			register "spdAddrLookup" = "
 			{
@@ -144,6 +143,7 @@ chip northbridge/amd/agesa/family14/root_complex
 				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
 			}"
 
-		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+		end # agesa northbridge
+
 	end #domain
 end #northbridge/amd/agesa/family14/root_complex