summaryrefslogtreecommitdiff
path: root/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-06-15 22:02:28 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-11-12 14:06:37 +0000
commitb9d2589ca40026b543ecb5b008ce0d1bc346bf53 (patch)
tree87cac45cfc1c1211f012aaa76b8a87162f092aff /src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
parent81dd52b7eb663c6098de5d8c7c56ed572c91b539 (diff)
downloadcoreboot-b9d2589ca40026b543ecb5b008ce0d1bc346bf53.tar.xz
mb/*/*: Harmonise FD and devicetree on boards featuring ICH7
On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb')
-rw-r--r--src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
index d4708c6059..63bcbc8d39 100644
--- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
@@ -131,9 +131,6 @@ chip northbridge/intel/x4x # Northbridge
device pci 1f.3 on # SMbus
subsystemid 0x1849 0x27da
end
- device pci 1f.4 off end
- device pci 1f.5 off end
- device pci 1f.6 off end
end
end
end