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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/asrock/g41c-gs/variants | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
| download | coreboot-fecf77770b8e68b9ef82021ca53c31db93736d93.tar.xz | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/variants')
5 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index acb8ac6702..b68aaa9fa7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -54,6 +54,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 805f2dac93..160d025ca7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index f4d1dc4291..0a8f27546d 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 2fd6e4f649..8119ced94c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -47,6 +47,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 5479faf3e9..e5e3cf9b90 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end |