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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 21:56:37 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 18:06:27 +0000
commit7843bd560e65b0a83e99b42bdd58dd6363656c56 (patch)
tree0d411ba99ae94da46d3fccaf09f1208fc812bb6f /src/mainboard/asrock/g41c-gs
parentc583920a748fb8bd7999142433ad08641b06283d (diff)
downloadcoreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.tar.xz
nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs')
-rw-r--r--src/mainboard/asrock/g41c-gs/Makefile.inc3
-rw-r--r--src/mainboard/asrock/g41c-gs/early_init.c (renamed from src/mainboard/asrock/g41c-gs/romstage.c)3
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc
index 82e72fbb81..ab352cb73d 100644
--- a/src/mainboard/asrock/g41c-gs/Makefile.inc
+++ b/src/mainboard/asrock/g41c-gs/Makefile.inc
@@ -1,4 +1,7 @@
ramstage-y += cstates.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c
+
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/early_init.c
index 06e13eb652..c7c7b730a6 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/early_init.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
@@ -27,7 +28,7 @@
#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
-void mb_lpc_setup(void)
+void bootblock_mainboard_early_init(void)
{
/* Set GPIOs on superio, enable UART */
if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {