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author | Michael Niewöhner <foss@mniewoehner.de> | 2019-09-23 14:38:41 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-02 11:15:00 +0000 |
commit | 6238563b2b65edac8e6dba4f8f20eb020c172317 (patch) | |
tree | 8293ac5ef0441b978b3c447a19f8262627d25843 /src/mainboard/asrock/h110m/ramstage.c | |
parent | 5387144a939b4ad3d334f2b4abebb987611b0274 (diff) | |
download | coreboot-6238563b2b65edac8e6dba4f8f20eb020c172317.tar.xz |
soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter
Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/h110m/ramstage.c')
-rw-r--r-- | src/mainboard/asrock/h110m/ramstage.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c3d4..a247b72587 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -24,6 +24,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } |