diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-19 12:31:21 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-21 07:16:01 +0000 |
commit | f50ea988b09e7201e129848ab64e6e0e69bf56c4 (patch) | |
tree | e7cf17631d7c3cd41fa3c68a4c578d4ee7e36b8a /src/mainboard/asrock/h110m | |
parent | dadcbfbe8c682c89b277fdbdfdd26cabd15fc20a (diff) | |
download | coreboot-f50ea988b09e7201e129848ab64e6e0e69bf56c4.tar.xz |
soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/asrock/h110m')
-rw-r--r-- | src/mainboard/asrock/h110m/include/gpio.h | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 193579c6a1..9b2193b587 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -12,13 +12,13 @@ static const struct pad_config gpio_table[] = { /* GPP_A0 - RCIN# */ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ @@ -28,9 +28,9 @@ static const struct pad_config gpio_table[] = { /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A11 - GPIO */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), /* GPP_A12 - GPIO */ @@ -40,7 +40,7 @@ static const struct pad_config gpio_table[] = { /* GPP_A14 - SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* GPP_A16 - GPIO */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), /* GPP_A17 - GPIO */ @@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B7 - NC */ PAD_NC(GPP_B7, NONE), /* GPP_B8 - GPIO */ - PAD_CFG_GPI_INT(GPP_B8, 5K_PU, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_B8, UP_5K, PLTRST, OFF), /* GPP_B9 - GPIO */ PAD_CFG_GPI_INT(GPP_B9, NONE, PLTRST, OFF), /* GPP_B10 - GPIO */ @@ -92,7 +92,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B13 - PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - SPKR */ - PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_B14, DN_20K, PLTRST, NF1), /* GPP_B15 - GPIO */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), /* GPP_B16 - GPIO */ @@ -110,7 +110,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B22 - GPIO */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), /* GPP_B23 - PCHHOT# */ - PAD_CFG_NF(GPP_B23, 20K_PD, PLTRST, NF2), + PAD_CFG_NF(GPP_B23, DN_20K, PLTRST, NF2), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ @@ -158,7 +158,7 @@ static const struct pad_config gpio_table[] = { /* GPP_C22 - UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), /* GPP_C23 - GPIO */ - PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, YES), + PAD_CFG_GPI_SCI_LOW(GPP_C23, NONE, DEEP, LEVEL), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -200,9 +200,9 @@ static const struct pad_config gpio_table[] = { /* GPP_D18 - GPIO */ PAD_CFG_GPI_INT(GPP_D18, NONE, PLTRST, OFF), /* GPP_D19 - DMIC_CLK0 */ - PAD_CFG_NF(GPP_D19, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_D19, UP_20K, PLTRST, NF1), /* GPP_D20 - DMIC_DATA0 */ - PAD_CFG_NF(GPP_D20, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_D20, UP_20K, PLTRST, NF1), /* GPP_D21 - GPIO */ PAD_CFG_GPI_INT(GPP_D21, NONE, PLTRST, OFF), /* GPP_D22 - GPIO */ @@ -212,11 +212,11 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - SATAXPCIE0 */ - PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1), /* GPP_E1 - SATAXPCIE1 */ - PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E1, UP_20K, PLTRST, NF1), /* GPP_E2 - SATAXPCIE2 */ - PAD_CFG_NF(GPP_E2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), /* GPP_E3 - CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, PLTRST, NF1), /* GPP_E4 - SATA_DEVSLP0 */ @@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = { /* GPP_F0 - GPIO */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), /* GPP_F1 - SATAXPCIE4 */ - PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, PLTRST, NF1), /* GPP_F2 - GPIO */ PAD_NC(GPP_F2, NONE), /* GPP_F3 - GPIO */ @@ -260,15 +260,15 @@ static const struct pad_config gpio_table[] = { /* GPP_F9 - GPIO */ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPP_F10 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F10, NONE, PLTRST), /* GPP_F11 - GPIO */ PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), /* GPP_F12 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), + PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST), /* GPP_F13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST), /* GPP_F14 - GPIO */ - PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), + PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP), /* GPP_F15 - USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* GPP_F16 - USB_OC5# */ @@ -304,7 +304,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G6 - GPIO */ _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G7 - GPIO */ @@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = { /* GPP_G12 - GPIO */ _PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G13 - GPIO */ @@ -328,17 +328,17 @@ static const struct pad_config gpio_table[] = { /* GPP_G14 - GPIO */ _PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | - PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | + PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT | PAD_BUF(TX_DISABLE), PAD_PULL(NONE)), /* GPP_G15 - GPIO */ PAD_CFG_GPO(GPP_G15, 0, PLTRST), /* GPP_G16 - GPIO */ - PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, DN_20K, PLTRST), /* GPP_G17 - GPIO */ PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), /* GPP_G18 - GPIO */ - PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_G18, NONE, PLTRST), /* GPP_G19 - SMI# */ PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), /* GPP_G20 - GPIO */ @@ -378,11 +378,11 @@ static const struct pad_config gpio_table[] = { /* GPP_H12 - GPIO */ PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), /* GPP_H13 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST), /* GPP_H14 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H14, NONE, PLTRST), /* GPP_H15 - GPIO */ - PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_APIC_HIGH(GPP_H15, NONE, PLTRST), /* GPP_H16 - GPIO */ PAD_CFG_GPI(GPP_H16, NONE, PLTRST), /* GPP_H17 - GPIO */ @@ -408,7 +408,7 @@ static const struct pad_config gpio_table[] = { /* GPD2 - LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* GPD3 - PWRBTN# */ - PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* GPD4 - SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* GPD5 - SLP_S4# */ @@ -444,15 +444,15 @@ static const struct pad_config gpio_table[] = { /* GPP_I5 - DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), /* GPP_I6 - DDPB_CTRLDATA */ - PAD_CFG_NF(GPP_I6, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, DN_20K, PLTRST, NF1), /* GPP_I7 - DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), /* GPP_I8 - DDPC_CTRLDATA */ - PAD_CFG_NF(GPP_I8, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1), /* GPP_I9 - DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), /* GPP_I10 - DDPD_CTRLDATA */ - PAD_CFG_NF(GPP_I10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1), }; /* Early pad configuration in romstage */ @@ -461,13 +461,13 @@ static const struct pad_config early_gpio_table[] = { /* GPP_A0 - RCIN# */ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), /* GPP_A1 - LAD0 */ - PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1), /* GPP_A2 - LAD1 */ - PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, PLTRST, NF1), /* GPP_A3 - LAD2 */ - PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, PLTRST, NF1), /* GPP_A4 - LAD3 */ - PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, PLTRST, NF1), /* GPP_A5 - LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), /* GPP_A6 - SERIRQ */ @@ -476,16 +476,16 @@ static const struct pad_config early_gpio_table[] = { /* GPP_A8 - CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, PLTRST, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, PLTRST, NF1), /* GPP_A13 - SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* GPP_A14 - SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - SUS_ACK# */ - PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), }; #endif |