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authorTristan Corrick <tristan@corrick.kiwi>2018-10-31 03:02:11 +1300
committerPatrick Georgi <pgeorgi@google.com>2018-11-16 10:05:26 +0000
commit3693294112a717aeb3f14db80f9e753dd376ca58 (patch)
tree64c25da486e7154a5ecb0d4b6749f7a45932532c /src/mainboard/asrock/h81m-hds/devicetree.cb
parentb2632cec0e6be1f90e209bbfd54a36287b862a08 (diff)
downloadcoreboot-3693294112a717aeb3f14db80f9e753dd376ca58.tar.xz
mainboard: Add ASRock H81M-HDS
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/asrock/h81m-hds/devicetree.cb')
-rw-r--r--src/mainboard/asrock/h81m-hds/devicetree.cb173
1 files changed, 173 insertions, 0 deletions
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
new file mode 100644
index 0000000000..32b5978092
--- /dev/null
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -0,0 +1,173 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/haswell
+ register "gpu_ddi_e_connected" = "1"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/haswell
+ register "c1_acpower" = "1"
+ register "c1_battery" = "1"
+ register "c2_acpower" = "3"
+ register "c2_battery" = "3"
+ register "c3_acpower" = "5"
+ register "c3_battery" = "5"
+
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x1849 0x0c00
+ end
+
+ device pci 01.0 on # PCIe graphics
+ subsystemid 0x1849 0x0c01
+ end
+
+ device pci 02.0 on # VGA controller
+ subsystemid 0x1849 0x0402
+ end
+
+ device pci 03.0 on # Mini-HD audio
+ subsystemid 0x1849 0x0c0c
+ end
+
+ chip southbridge/intel/lynxpoint
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x80"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8a"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x8a"
+
+ register "sata_ahci" = "1"
+ register "sata_port_map" = "0x33"
+
+ register "gen1_dec" = "0x00000295" # Super I/O HWM
+
+ device pci 14.0 on # xHCI controller
+ subsystemid 0x1849 0x8c31
+ end
+ device pci 16.0 on # Management Engine interface 1
+ subsystemid 0x1849 0x8c3a
+ end
+ device pci 16.1 off end # Management Engine interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on # EHCI controller #2
+ subsystemid 0x1849 0x8c2d
+ end
+ device pci 1b.0 on # HD audio controller
+ subsystemid 0x1849 0x7662
+ end
+ device pci 1c.0 on # PCIe port #1
+ subsystemid 0x1849 0x8c10
+ end
+ device pci 1c.1 off end # PCIe port #2
+ device pci 1c.2 off end # PCIe port #3
+ device pci 1c.3 on # Realtek Gigabit Ethernet
+ subsystemid 0x1849 0x8c16
+ chip drivers/net
+ register "customized_leds" = "0x0824"
+ device pci 00.0 on
+ subsystemid 0x1849 0x8168
+ end
+ end
+ end
+ device pci 1c.4 on # ASMedia USB controller
+ subsystemid 0x1849 0x8c18
+ device pci 00.0 on
+ subsystemid 0x1849 0x1042
+ end
+ end
+ device pci 1c.5 on # PCIe 1x slot
+ subsystemid 0x1849 0x8c1a
+ end
+ device pci 1c.6 off end # PCIe port #7
+ device pci 1c.7 off end # PCIe port #8
+ device pci 1d.0 on # EHCI controller #1
+ subsystemid 0x1849 0x8c26
+ end
+ device pci 1f.0 on # LPC bridge
+ subsystemid 0x1849 0x8c5c
+
+ chip superio/nuvoton/nct6776
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # Parallel
+ io 0x60 = 0x0378
+ irq 0x70 = 7
+ drq 0x74 = 4 # No DMA
+ irq 0xf0 = 0x3c # Printer mode
+ end
+ device pnp 2e.2 on # UART A
+ io 0x60 = 0x03f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # IR
+ io 0x60 = 0x02f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # PS/2 KBC
+ io 0x60 = 0x0060
+ io 0x62 = 0x0064
+ irq 0x70 = 1 # Keyboard
+ irq 0x72 = 12 # Mouse
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GPIO8
+ device pnp 2e.107 off end # GPIO9
+ device pnp 2e.8 off end # WDT
+ device pnp 2e.108 off end # GPIO0
+ device pnp 2e.208 off end # GPIOA
+ device pnp 2e.308 off end # GPIO base
+ device pnp 2e.109 off end # GPIO1
+ device pnp 2e.209 off end # GPIO2
+ device pnp 2e.309 off end # GPIO3
+ device pnp 2e.409 off end # GPIO4
+ device pnp 2e.509 off end # GPIO5
+ device pnp 2e.609 off end # GPIO6
+ device pnp 2e.709 off end # GPIO7
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HWM, LED
+ io 0x60 = 0x0290
+ io 0x62 = 0
+ irq 0x70 = 0
+ end
+ device pnp 2e.d off end # VID
+ device pnp 2e.e off end # CIR wake-up
+ device pnp 2e.f off end # GPIO PP/OD
+ device pnp 2e.14 off end # SVID
+ device pnp 2e.16 off end # Deep sleep
+ device pnp 2e.17 off end # GPIOA
+ end
+ end
+ device pci 1f.2 on # SATA controller 1
+ subsystemid 0x1849 0x8c02
+ end
+ device pci 1f.3 on # SMBus
+ subsystemid 0x1849 0x8c22
+ end
+ device pci 1f.5 off end # SATA controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end