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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-22 15:24:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-28 17:24:48 +0200
commitcdfb46240b4bba8a112c85a5f5d26447e90378b3 (patch)
treed344b5c2916050e49975a3089ae81bb3c7a6c632 /src/mainboard/asrock/imb-a180
parente5523b808b2a29a3049a21a3b0339e80fbeef42a (diff)
downloadcoreboot-cdfb46240b4bba8a112c85a5f5d26447e90378b3.tar.xz
AGESA boards: Use devicetree for PCI bus enumeration
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/asrock/imb-a180')
-rw-r--r--src/mainboard/asrock/imb-a180/mptable.c44
1 files changed, 21 insertions, 23 deletions
diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c
index a8326a02a4..11da1309a0 100644
--- a/src/mainboard/asrock/imb-a180/mptable.c
+++ b/src/mainboard/asrock/imb-a180/mptable.c
@@ -29,8 +29,6 @@
#include "southbridge/amd/agesa/hudson/hudson.h" /* pm_ioread() */
#define IO_APIC_ID CONFIG_MAX_CPUS
-extern u8 bus_yangtze[6];
-
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
@@ -189,27 +187,27 @@ static void *smp_write_config_table(void *v)
/* on board NIC & Slot PCIE. */
/* PCI slots */
- /* PCI_SLOT 0. */
- PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
- PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
- PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
- PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
-
- /* PCI_SLOT 1. */
- PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
- PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
- PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
- PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
-
- /* PCI_SLOT 2. */
- PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
- PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
- PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
- PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
-
- PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
- PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
- PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+
+ /* PCI_SLOT 1. */
+ PCI_INT(bus_pci, 0x6, 0x0, 0x15);
+ PCI_INT(bus_pci, 0x6, 0x1, 0x16);
+ PCI_INT(bus_pci, 0x6, 0x2, 0x17);
+ PCI_INT(bus_pci, 0x6, 0x3, 0x14);
+
+ /* PCI_SLOT 2. */
+ PCI_INT(bus_pci, 0x7, 0x0, 0x16);
+ PCI_INT(bus_pci, 0x7, 0x1, 0x17);
+ PCI_INT(bus_pci, 0x7, 0x2, 0x14);
+ PCI_INT(bus_pci, 0x7, 0x3, 0x15);
+ }
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);