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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-09-09 12:06:16 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-01-14 21:45:39 +0000 |
| commit | 106a3e8c7a3e0aba9d6e5a9c171d0e999063951a (patch) | |
| tree | 15e8027085e723316212baa0944a1c0e53117e95 /src/mainboard/asrock | |
| parent | ffdd33c312cf5ea895c1dad522edb603801d4c37 (diff) | |
| download | coreboot-106a3e8c7a3e0aba9d6e5a9c171d0e999063951a.tar.xz | |
mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21464
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e9000a6fa7..4498b10706 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -75,6 +75,7 @@ static void ich7_enable_lpc(void) /* Decode range */ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); } void mainboard_romstage_entry(unsigned long bist) |