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authorElyes HAOUAS <ehaouas@noos.fr>2020-10-08 09:10:37 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-28 21:33:12 +0000
commit3555b2f9f381ba753426a15a738b3725abae3a2f (patch)
tree56804003563f7ae5f98f4761c80ce03de8d66b01 /src/mainboard/asrock
parentbebe4fbf40b9135b05d72fc35351899ba9e4c041 (diff)
downloadcoreboot-3555b2f9f381ba753426a15a738b3725abae3a2f.tar.xz
mb/asrock/e350m1: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' are identical. Change-Id: Ief7ea77f8081cd6b7fb18fbf1d25c7394daca07d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46154 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/acpi/mainboard.asl12
-rw-r--r--src/mainboard/asrock/e350m1/acpi/sata.asl24
-rw-r--r--src/mainboard/asrock/e350m1/acpi/sleep.asl32
-rw-r--r--src/mainboard/asrock/e350m1/acpi/usb_oc.asl82
4 files changed, 75 insertions, 75 deletions
diff --git a/src/mainboard/asrock/e350m1/acpi/mainboard.asl b/src/mainboard/asrock/e350m1/acpi/mainboard.asl
index e4a0c799fe..a1eb03b469 100644
--- a/src/mainboard/asrock/e350m1/acpi/mainboard.asl
+++ b/src/mainboard/asrock/e350m1/acpi/mainboard.asl
@@ -18,20 +18,20 @@ Name(PICM, One) /* Assume APIC */
Scope(\_SB) {
Method(OSFL, 0){
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+ if (OSVR != Ones) {Return (OSVR)} /* OS version was already detected */
if(CondRefOf(\_OSI))
{
- Store(1, OSVR) /* Assume some form of XP */
+ OSVR = 1 /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */
{
- Store(2, OSVR)
+ OSVR = 2
}
} else {
- If(WCMP(\_OS,"Linux")) {
- Store(3, OSVR) /* Linux */
+ If (WCMP(\_OS,"Linux")) {
+ OSVR = 3 /* Linux */
} Else {
- Store(4, OSVR) /* Gotta be WinCE */
+ OSVR = 4 /* Gotta be WinCE */
}
}
Return(OSVR)
diff --git a/src/mainboard/asrock/e350m1/acpi/sata.asl b/src/mainboard/asrock/e350m1/acpi/sata.asl
index 7f305fb17f..6d9ff03005 100644
--- a/src/mainboard/asrock/e350m1/acpi/sata.asl
+++ b/src/mainboard/asrock/e350m1/acpi/sata.asl
@@ -35,7 +35,7 @@ Device(PMRY)
Device(PMST) {
Name(_ADR, 0)
Method(_STA,0) {
- if (LGreater(P0IS,0)) {
+ if (P0IS > 0) {
return (0x0F) /* sata is visible */
}
else {
@@ -48,7 +48,7 @@ Device(PMRY)
{
Name(_ADR, 1)
Method(_STA,0) {
- if (LGreater(P1IS,0)) {
+ if (P1IS > 0) {
return (0x0F) /* sata is visible */
}
else {
@@ -71,7 +71,7 @@ Device(SEDY)
{
Name(_ADR, 0)
Method(_STA,0) {
- if (LGreater(P2IS,0)) {
+ if (P2IS > 0) {
return (0x0F) /* sata is visible */
}
else {
@@ -84,7 +84,7 @@ Device(SEDY)
{
Name(_ADR, 1)
Method(_STA,0) {
- if (LGreater(P3IS,0)) {
+ if (P3IS > 0) {
return (0x0F) /* sata is visible */
}
else {
@@ -98,35 +98,35 @@ Device(SEDY)
Scope(\_GPE) {
Method(_L1F,0x0,NotSerialized) {
if (\_SB.P0PR) {
- if (LGreater(\_SB.P0IS,0)) {
+ if (\_SB.P0IS > 0) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P0PR)
+ \_SB.P0PR = 1
}
if (\_SB.P1PR) {
- if (LGreater(\_SB.P1IS,0)) {
+ if (\_SB.P1IS > 0) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P1PR)
+ \_SB.P1PR = 1
}
if (\_SB.P2PR) {
- if (LGreater(\_SB.P2IS,0)) {
+ if (\_SB.P2IS > 0) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P2PR)
+ \_SB.P2PR = 1
}
if (\_SB.P3PR) {
- if (LGreater(\_SB.P3IS,0)) {
+ if (\_SB.P3IS > 0) {
sleep(32)
}
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
- store(one, \_SB.P3PR)
+ \_SB.P3PR = 1
}
}
}
diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl
index 76b5f9edc6..3b6fd02055 100644
--- a/src/mainboard/asrock/e350m1/acpi/sleep.asl
+++ b/src/mainboard/asrock/e350m1/acpi/sleep.asl
@@ -26,23 +26,23 @@ Method(\_PTS, 1) {
/* DBGO("\n") */
/* Don't allow PCIRST# to reset USB */
- if (LEqual(Arg0,3)){
- Store(0,URRE)
+ if (Arg0 == 3){
+ URRE = 0
}
/* Clear sleep SMI status flag and enable sleep SMI trap. */
- /*Store(One, CSSM)
- Store(One, SSEN)*/
+ /*CSSM = 1
+ SSEN = 1*/
/* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
+ /*if (\_SB.SBRI <= 0x13) {
+ * \_SB.PWDE = 0
*}
*/
/* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
+ WKST [0] = 0
+ WKST [1] = 0
} /* End Method(\_PTS) */
/*
@@ -67,21 +67,21 @@ Method(\_WAK, 1) {
/* DBGO(" to S0\n") */
/* Re-enable HPET */
- Store(1,HPDE)
+ HPDE = 1
/* Restore PCIRST# so it resets USB */
- if (LEqual(Arg0,3)){
- Store(1,URRE)
+ if (Arg0 == 3){
+ URRE = 1
}
/* Arbitrarily clear PciExpWakeStatus */
- Store(PWST, Local1)
- Store(Local1, PWST)
+ Local1 = PWST
+ PWST = Local1
- /* if (DeRefOf(Index(WKST,0))) {
- * Store(0, Index(WKST,1))
+ /* if (DeRefOf(WKST [0])) {
+ * WKST [1] = 0
* } else {
- * Store(Arg0, Index(WKST,1))
+ * WKST [1] = Arg0
* }
*/
Return(WKST)
diff --git a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
index 4ecc52ade9..e4ed275617 100644
--- a/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
+++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
@@ -14,134 +14,134 @@ Name(UOM9, 6)
Method(UCOC, 0) {
Sleep(20)
- Store(0x13,CMTI)
- Store(0,GPSL)
+ CMTI = 0x13
+ GPSL = 0
}
/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
+If (UOM0 <= 9) {
Scope (\_GPE) {
Method (_L13) {
UCOC()
- if(LEqual(GPB0,PLC0)) {
- Not(PLC0,PLC0)
- Store(PLC0, \_SB.PT0D)
+ if (GPB0 == PLC0) {
+ PLC0 = ~PLC0
+ \_SB.PT0D = PLC0
}
}
}
}
/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
+If (UOM1 <= 9) {
Scope (\_GPE) {
Method (_L14) {
UCOC()
- if (LEqual(GPB1,PLC1)) {
- Not(PLC1,PLC1)
- Store(PLC1, \_SB.PT1D)
+ if (GPB1 == PLC1) {
+ PLC1 = ~PLC1
+ \_SB.PT1D = PLC1
}
}
}
}
/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
+If (UOM2 <= 9) {
Scope (\_GPE) {
Method (_L15) {
UCOC()
- if (LEqual(GPB2,PLC2)) {
- Not(PLC2,PLC2)
- Store(PLC2, \_SB.PT2D)
+ if (GPB2 == PLC2) {
+ PLC2 = ~PLC2
+ \_SB.PT2D = PLC2
}
}
}
}
/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
+If (UOM3 <= 9) {
Scope (\_GPE) {
Method (_L16) {
UCOC()
- if (LEqual(GPB3,PLC3)) {
- Not(PLC3,PLC3)
- Store(PLC3, \_SB.PT3D)
+ if (GPB3 == PLC3) {
+ PLC3 = ~PLC3
+ \_SB.PT3D = PLC3
}
}
}
}
/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
+If (UOM4 <= 9) {
Scope (\_GPE) {
Method (_L19) {
UCOC()
- if (LEqual(GPB4,PLC4)) {
- Not(PLC4,PLC4)
- Store(PLC4, \_SB.PT4D)
+ if (GPB4 == PLC4) {
+ PLC4 = ~PLC4
+ \_SB.PT4D = PLC4
}
}
}
}
/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
+If (UOM5 <= 9) {
Scope (\_GPE) {
Method (_L1A) {
UCOC()
- if (LEqual(GPB5,PLC5)) {
- Not(PLC5,PLC5)
- Store(PLC5, \_SB.PT5D)
+ if (GPB5 == PLC5) {
+ PLC5 = ~PLC5
+ \_SB.PT5D = PLC5
}
}
}
}
/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
+If (UOM6 <= 9) {
Scope (\_GPE) {
/* Method (_L1C) { */
Method (_L06) {
UCOC()
- if (LEqual(GPB6,PLC6)) {
- Not(PLC6,PLC6)
- Store(PLC6, \_SB.PT6D)
+ if (GPB6 == PLC6) {
+ PLC6 = ~PLC6
+ \_SB.PT6D = PLC6
}
}
}
}
/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
+If (UOM7 <= 9) {
Scope (\_GPE) {
/* Method (_L1D) { */
Method (_L07) {
UCOC()
- if (LEqual(GPB7,PLC7)) {
- Not(PLC7,PLC7)
- Store(PLC7, \_SB.PT7D)
+ if (GPB7 == PLC7) {
+ PLC7 = ~PLC7
+ \_SB.PT7D = PLC7
}
}
}
}
/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
+If (UOM8 <= 9) {
Scope (\_GPE) {
Method (_L17) {
- if (LEqual(G8IS,PLC8)) {
- Not(PLC8,PLC8)
- Store(PLC8, \_SB.PT8D)
+ if (G8IS == PLC8) {
+ PLC8 = ~PLC8
+ \_SB.PT8D = PLC8
}
}
}
}
/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
+If (UOM9 <= 9) {
Scope (\_GPE) {
Method (_L0E) {
- if (LEqual(G9IS,0)) {
- Store(1,\_SB.PT9D)
+ if (G9IS == 0) {
+ \_SB.PT9D = 1
}
}
}