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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-04 16:08:33 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-05-07 20:59:26 +0000 |
| commit | 94bbf0efc8ad69e18997dbb037b1609ff59aab32 (patch) | |
| tree | ee28e95a974a3bcfe0cfc22535f6caa3ca6ca7fc /src/mainboard/asrock | |
| parent | b6796be8e0936569c9eaf89e479549457dfb06ec (diff) | |
| download | coreboot-94bbf0efc8ad69e18997dbb037b1609ff59aab32.tar.xz | |
skylake DT/HALO mainboards: Drop `SaGv` setting
SaGv is only supported on ULT/ULX hardware.
Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/h110m/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 74e5720b0c..0acba3aaf4 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -19,7 +19,6 @@ chip soc/intel/skylake # FSP Configuration register "PrimaryDisplay" = "Display_PEG" - register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |