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authorSumeet R Pawnikar <sumeet.r.pawnikar@intel.com>2020-05-10 01:24:11 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-18 07:13:23 +0000
commit97c5464443306f26b61cec3a0f50108a5c06b7ef (patch)
treef085457907ad200a0d9d9be8a07c937e755fae91 /src/mainboard/asrock
parent19c2ce7639d55908d210782ae5a0315396cc7eaf (diff)
downloadcoreboot-97c5464443306f26b61cec3a0f50108a5c06b7ef.tar.xz
skylake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Skylake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on nami system Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9ff8ceb62d..254eff853c 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -247,7 +247,9 @@ chip soc/intel/skylake
register "PcieRpHotPlug[6]" = "1"
# PL2 override 91W
- register "tdp_pl2_override" = "91"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 91,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"