AMD F14 southbridge update

This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

9 files changed, 269 insertions, 149 deletions

diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index e6153c01f2..c60f6dfca4 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -47,10 +47,6 @@ config AMD_AGESA
         bool
         default y
 
-config AMD_CIMX_SB800
-        bool
-        default y
-
 config MAINBOARD_DIR
         string
         default asrock/e350m1
diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc
index 0f17032e4c..22d8373600 100644
--- a/src/mainboard/asrock/e350m1/Makefile.inc
+++ b/src/mainboard/asrock/e350m1/Makefile.inc
@@ -30,6 +30,5 @@ ramstage-y += BiosCallOuts.c
 ramstage-y += PlatformGnbPcie.c
 
 ramstage-y += reset.c
-ramstage-y += pmio.c
 
 subdirs-$(CONFIG_AMD_AGESA) += ../../../vendorcode/amd/agesa/f14
diff --git a/src/mainboard/asrock/e350m1/fadt.c b/src/mainboard/asrock/e350m1/fadt.c
index 0b37885955..020d011fdf 100644
--- a/src/mainboard/asrock/e350m1/fadt.c
+++ b/src/mainboard/asrock/e350m1/fadt.c
@@ -28,27 +28,14 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-//#include "../../../southbridge/amd/sb800/sb800.h"
-
-/*extern*/ u16 pm_base = 0x800;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb800. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
-
-#define ACPI_PM_EVT_BLK		(pm_base + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(pm_base + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK	(pm_base + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK		(pm_base + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK		(pm_base + 0x10) /* 8 bytes */
-#define ACPI_CPU_CONTORL	(pm_base + 0x08) /* 6 bytes */
+#include "SBPLATFORM.h"
+
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
+	u16 val = 0;
 	acpi_header_t *header = &(fadt->header);
 
-	pm_base &= 0xFFFF;
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
@@ -71,38 +58,38 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 
-	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
-	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
-	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
-	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
-	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
-	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
-	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
-	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
+	val = PM1_EVT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
+	val = PM1_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
+	val = PM1_TMR_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
+	val = GPE0_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
 
 	/* CpuControl is in \_PR.CPU0, 6 bytes */
-	pm_iowrite(0x66, ACPI_CPU_CONTORL & 0xFF);
-	pm_iowrite(0x67, ACPI_CPU_CONTORL >> 8);
-
-	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
-	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
-
-	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
+	val = CPU_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
+	val = 0;
+	WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
+	val = ACPI_PMA_CNT_BLK_ADDRESS;
+	WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
+
+	/* AcpiDecodeEnable, When set, SB uses the contents of the
+	 * PM registers at index 60-6B to decode ACPI I/O address.
+	 * AcpiSmiEn & SmiCmdEn*/
+	val = BIT0 | BIT1 | BIT2 | BIT4;
+	WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
 
-	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
-					* the contents of the PM registers at
-					* index 60-6B to decode ACPI I/O address.
-					* AcpiSmiEn & SmiCmdEn*/
 	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	outl(0x1, PM1_CNT_BLK_ADDRESS);		  /* set SCI_EN */
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
 	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
 	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
 	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
 
 	fadt->pm1_evt_len = 4;
@@ -145,7 +132,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_evt_blk.bit_width = 32;
 	fadt->x_pm1a_evt_blk.bit_offset = 0;
 	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 	fadt->x_pm1a_evt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_evt_blk.space_id = 1;
@@ -160,7 +147,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
 	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -175,7 +162,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm2_cnt_blk.bit_width = 0;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
 	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
 
@@ -183,7 +170,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
 	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
 
@@ -191,7 +178,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_gpe0_blk.bit_width = 32;
 	fadt->x_gpe0_blk.bit_offset = 0;
 	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 	fadt->x_gpe0_blk.addrh = 0x0;
 
 
diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c
index cc7fb5d522..43867172d5 100644
--- a/src/mainboard/asrock/e350m1/get_bus_conf.c
+++ b/src/mainboard/asrock/e350m1/get_bus_conf.c
@@ -24,6 +24,9 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <cpu/amd/amdfam14.h>
+#if CONFIG_AMD_SB_CIMX
+#include "sb_cimx.h"
+#endif
 
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -127,4 +130,8 @@ void get_bus_conf(void)
   bus_isa = 10;
   apicid_base = CONFIG_MAX_CPUS;
   apicid_sb800 = apicid_base;
+
+#if CONFIG_AMD_SB_CIMX
+	sb_Late_Post();
+#endif
 }
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index e286e6f08e..05c2275497 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -24,6 +24,7 @@
 #include <arch/io.h>
 #include <string.h>
 #include <stdint.h>
+#include <SBPLATFORM.h>
 
 extern u8 bus_sb800[2];
 
@@ -64,11 +65,8 @@ static void *smp_write_config_table(void *v)
   u32 dword;
   u8 byte;
     
-  dword = 0;
-  dword = pm_ioread(0x34) & 0xF0;
-  dword |= (pm_ioread(0x35) & 0xFF) << 8;
-  dword |= (pm_ioread(0x36) & 0xFF) << 16;
-  dword |= (pm_ioread(0x37) & 0xFF) << 24;
+  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+  dword &= 0xFFFFFFF0;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
new file mode 100644
index 0000000000..6e0faea633
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -0,0 +1,222 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _E350M1_CFG_H_
+#define _E350M1_CFG_H_
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M			0
+#define BIOS_SIZE_2M			1
+#define BIOS_SIZE_4M			3
+#define BIOS_SIZE_8M			7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+  #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+  #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+  #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+  #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM			0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER			1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CONFIG		0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL			0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#define SATA_CONTROLLER		CIMX_OPTION_ENABLED
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_MODE			NATIVE_IDE_MODE
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE			0
+#define IDE_NATIVE_MODE			1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#define SATA_IDE_MODE			IDE_LEGACY_MODE
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK		0x00
+#define INTERNAL_CLOCK		0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE	INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED	1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO			0
+#define AZALIA_DISABLE			1
+#define AZALIA_ENABLE			2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#define AZALIA_CONTROLLER		AZALIA_AUTO
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#define AZALIA_PIN_CONFIG		1
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+//#define AZALIA_SDIN_PIN		0xAA
+#define AZALIA_SDIN_PIN			0x2A
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#define GPP_CONTROLLER			CIMX_OPTION_ENABLED
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#define GPP_CFGMODE			GPP_CFGMODE_X1111
+
+/**
+ * @def NB_SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define NB_SB_GEN2			TRUE
+
+/**
+ * @def SB_GEN2
+ *    0  - Disable
+ *    1  - Enable
+ */
+#define SB_GPP_GEN2			TRUE
+
+
+/**
+ * @def   GEC_CONFIG
+ *    0  - Enable
+ *    1  - Disable
+ */
+#define GEC_CONFIG			0
+
+#endif
diff --git a/src/mainboard/asrock/e350m1/pmio.c b/src/mainboard/asrock/e350m1/pmio.c
deleted file mode 100644
index baded54ba6..0000000000
--- a/src/mainboard/asrock/e350m1/pmio.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-#include <arch/io.h>	/*inb, outb*/
-#include "pmio.h"
-
-static void pmio_write_index(u16 port_base, u8 reg, u8 value)
-{
-	outb(reg, port_base);
-	outb(value, port_base + 1);
-}
-
-static u8 pmio_read_index(u16 port_base, u8 reg)
-{
-	outb(reg, port_base);
-	return inb(port_base + 1);
-}
-
-void pm_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM_INDEX, reg, value);
-}
-
-u8 pm_ioread(u8 reg)
-{
-	return pmio_read_index(PM_INDEX, reg);
-}
-
-void pm2_iowrite(u8 reg, u8 value)
-{
-	pmio_write_index(PM2_INDEX, reg, value);
-}
-
-u8 pm2_ioread(u8 reg)
-{
-	return pmio_read_index(PM2_INDEX, reg);
-}
-
diff --git a/src/mainboard/asrock/e350m1/pmio.h b/src/mainboard/asrock/e350m1/pmio.h
deleted file mode 100644
index 207fdc24ab..0000000000
--- a/src/mainboard/asrock/e350m1/pmio.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-#ifndef _PMIO_H_
-#define _PMIO_H_
-
-#define PM_INDEX	0xCD6
-#define PM_DATA		0xCD7
-#define PM2_INDEX	0xCD0
-#define PM2_DATA	0xCD1
-
-void pm_iowrite(u8 reg, u8 value);
-u8 pm_ioread(u8 reg);
-void pm2_iowrite(u8 reg, u8 value);
-u8 pm2_ioread(u8 reg);
-
-#endif
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 38790cd517..133aca7350 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -35,7 +35,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "pc80/i8254.c"
 #include "pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
 #include "SBPLATFORM.h"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
@@ -57,7 +57,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
-		sb_poweron_init();
+		sb_Poweron_Init();
 
 		post_code(0x31);
 		w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);