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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 17:00:52 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-19 11:20:06 +0000 |
| commit | 90ae08922d7f6fdc8b762cb7bc1e2d8d85807854 (patch) | |
| tree | e0761159e52252c6e224900a8bf4ca350a160dcd /src/mainboard/asrock | |
| parent | afc6c0ae12ddd26c05bcc2fa527c7a15d0bca0ad (diff) | |
| download | coreboot-90ae08922d7f6fdc8b762cb7bc1e2d8d85807854.tar.xz | |
nb/intel/haswell: Consolidate memory-down SPD handling
Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.
Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/romstage.c | 10 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 6 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 1c17fcb909..7a4e402d91 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -17,12 +17,12 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(uint8_t spd_map[4]) +void mb_get_spd_map(struct spd_info *spdi) { - spd_map[0] = 0xa0; - spd_map[1] = 0xa2; - spd_map[2] = 0xa4; - spd_map[3] = 0xa6; + spdi->addresses[0] = 0xa0; + spdi->addresses[1] = 0xa2; + spdi->addresses[2] = 0xa4; + spdi->addresses[3] = 0xa6; } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 16b1500bd6..58f9697162 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -17,10 +17,10 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mb_get_spd_map(uint8_t spd_map[4]) +void mb_get_spd_map(struct spd_info *spdi) { - spd_map[0] = 0xa0; - spd_map[2] = 0xa4; + spdi->addresses[0] = 0xa0; + spdi->addresses[2] = 0xa4; } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |