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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-05-06 23:53:09 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 10:03:38 +0200
commite61dd0f7a2be83ce5ba87d74f7384111576ffd49 (patch)
treea9f2c51500bbd8702cf039c8e620653d25c4b4d8 /src/mainboard/asrock
parent216a619a74d61f66e3d3e1d668028d11a8868b4d (diff)
downloadcoreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.tar.xz
southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c10
-rw-r--r--src/mainboard/asrock/imb-a180/romstage.c9
2 files changed, 0 insertions, 19 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index ba2e34dfda..2913c08da0 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -35,8 +35,6 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/lapic.h"
-#include "drivers/pc80/i8254.c"
-#include "drivers/pc80/i8259.c"
#include <sb_cimx.h>
#include "SBPLATFORM.h"
@@ -115,14 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
else
printk(BIOS_DEBUG, "passed.\n");
- /* Initialize i8259 pic */
- post_code(0x41);
- setup_i8259();
-
- /* Initialize i8254 timers */
- post_code(0x42);
- setup_i8254();
-
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 59d95f9e0f..5b64cf9c05 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -34,8 +34,6 @@
#include "cpu/x86/lapic.h"
#include "southbridge/amd/agesa/hudson/hudson.h"
#include "cpu/amd/agesa/s3_resume.h"
-#include "src/drivers/pc80/i8254.c"
-#include "src/drivers/pc80/i8259.c"
#include "cbmem.h"
#include "superio/winbond/w83627uhg/early_serial.c"
@@ -184,13 +182,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
outb(0xEA, 0xCD6);
outb(0x1, 0xcd7);
- /* Initialize i8259 pic */
- post_code(0x41);
- setup_i8259 ();
-
- /* Initialize i8254 timers */
- post_code(0x42);
- setup_i8254 ();
post_code(0x50);
copy_and_run();