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authorStefan Reinauer <reinauer@chromium.org>2013-03-21 11:51:41 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-22 00:00:09 +0100
commit24d1d4b47274eb82893e6726472a991a36fce0aa (patch)
tree57126316330f6f9d407f605fa831ce530650f069 /src/mainboard/asrock
parent55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff)
downloadcoreboot-24d1d4b47274eb82893e6726472a991a36fce0aa.tar.xz
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c1
-rw-r--r--src/mainboard/asrock/e350m1/reset.c7
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c1
3 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 46b6ab0305..74a5412caf 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
diff --git a/src/mainboard/asrock/e350m1/reset.c b/src/mainboard/asrock/e350m1/reset.c
index 5958e772dd..bb2482b57b 100644
--- a/src/mainboard/asrock/e350m1/reset.c
+++ b/src/mainboard/asrock/e350m1/reset.c
@@ -17,10 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
+#include <arch/io.h>
#include <reset.h>
-#include <arch/io.h> /*inb, outb*/
-#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 3a1e7aa0d2..79f963b529 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -24,7 +24,6 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>