mb/*/*: use ACPIMMIO common block wherever possible

TEST=boot PC Engines apu2 and launch Debian Linux

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

3 files changed, 79 insertions, 93 deletions

diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 5d7211c3e6..c9ecad746a 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -15,6 +15,7 @@
 
 #include <AGESA.h>
 #include <amdlib.h>
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 
@@ -34,88 +35,81 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
-/*  Call the host environment interface to provide a user hook opportunity. */
+/* Call the host environment interface to provide a user hook opportunity. */
 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
+	AGESA_STATUS       Status;
+	UINTN              FcnData;
+	MEM_DATA_STRUCT    *MemData;
+	UINT32             AcpiMmioAddr;
+	UINT32             GpioMmioAddr;
+	UINT8              Data8;
+	UINT8              TempData8;
 
-  FcnData = Data;
-  MemData = ConfigPtr;
+	FcnData = Data;
+	MemData = ConfigPtr;
 
-  Status  = AGESA_SUCCESS;
-  /* Get SB800 MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8 << 8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_SUCCESS;
+	AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
 
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
 
-  /* this seems to be just copy-pasted from the AMD reference boards and needs
-   * some investigation
-   */
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  // disable memory clear for boot time reduction
-  MemData->ParameterListPtr->EnableMemClr = FALSE;
-  return Status;
+	/*
+	 * this seems to be just copy-pasted from the AMD reference boards and
+	 * needs some investigation
+	 */
+	switch (MemData->ParameterListPtr->DDR3Voltage) {
+	case VOLT1_35:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_25:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		break;
+	case VOLT1_5:
+	default:
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 |= (UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Data8 &= ~(UINT8)BIT6;
+		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	/* disable memory clear for boot time reduction */
+	MemData->ParameterListPtr->EnableMemClr = FALSE;
+	return Status;
 }
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index e2f4f2b259..96744a39bd 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -26,19 +26,17 @@ static void mainboard_enable(struct device *dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 
-	/* Power off unused clock pins of GPP PCIe devices */
-	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
-	/*
+	/* Power off unused clock pins of GPP PCIe devices
 	 * GPP CLK0 connected to unpopulated mini PCIe slot
 	 * GPP CLK1 connected to ethernet chip
 	 */
-	write8(misc_mem_clk_cntrl + 0, 0xFF);
+	misc_write8(0, 0xff);
 	/* GPP CLK2 connected to the external USB3 controller */
-	write8(misc_mem_clk_cntrl + 1, 0x0F);
-	write8(misc_mem_clk_cntrl + 2, 0x00);
-	write8(misc_mem_clk_cntrl + 3, 0x00);
+	misc_write8(1, 0x0f);
+	misc_write8(2, 0);
+	misc_write8(3, 0);
 	/* SLT_GFX_CLK connected to PCIe slot */
-	write8(misc_mem_clk_cntrl + 4, 0xF0);
+	misc_write8(4, 0xf0);
 
 	/*
 	 * Initialize ASF registers to an arbitrary address because someone
diff --git a/src/mainboard/asrock/imb-a180/bootblock.c b/src/mainboard/asrock/imb-a180/bootblock.c
index eb5641ff5e..e87dc21f87 100644
--- a/src/mainboard/asrock/imb-a180/bootblock.c
+++ b/src/mainboard/asrock/imb-a180/bootblock.c
@@ -21,20 +21,14 @@
 
 void bootblock_mainboard_early_init(void)
 {
-	u32 reg32;
-
 	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
 	pm_write8(0xea, 0x1);
 
 	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
-	reg32 = misc_read32(0x28);
-	reg32 &= 0xfff8ffff;
-	misc_write32(0x28, reg32);
+	misc_write32(0x28, misc_read32(0x28) & 0xfff8ffff);
 
 	/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
-	reg32 = misc_read32(0x40);
-	reg32 &= 0xffffbffb;
-	misc_write32(0x40, reg32);
+	misc_write32(0x40, misc_read32(0x40) & 0xffffbffb);
 
 	/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);