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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2018-07-30 12:31:00 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-08-04 15:20:12 +0000 |
| commit | 6837769a9028f91b502bab98ae30b9167ca8837f (patch) | |
| tree | d5ebc7bb6904aa20516590d5aa00c6b15ca48e88 /src/mainboard/asrock | |
| parent | a4432f469a97b4279cb53b79acd5c835e0880981 (diff) | |
| download | coreboot-6837769a9028f91b502bab98ae30b9167ca8837f.tar.xz | |
mb/pcengines/apu2: turn LED 2 and LED 3 off in final stage
Due to vendor's requirements LED 2 and LED 3 should be turned
off in late boot process. Add appropriate functions to read and
write GPIO status.
Change-Id: Ia286ef7d02cfcefacf0e8d358847406efe1496fb
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock')
0 files changed, 0 insertions, 0 deletions