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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-06-26 11:17:37 +0300
committerNico Huber <nico.h@gmx.de>2019-06-27 10:20:02 +0000
commite6a491e782a2abdddd035b370ab9cc3165f5230c (patch)
treef4ca7696cef5e0acf5a6b7bb38a70814255ec17d /src/mainboard/asrock
parent804a0433e0a793876b954ad162f6efeef8f9a5d6 (diff)
downloadcoreboot-e6a491e782a2abdddd035b370ab9cc3165f5230c.tar.xz
mb/asrock/h110m: set serirq_mode to continuous mode
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port from the SurerIO chip don't work correctly after the LPC controller (PCI 0:1f.0) initialization. Console output is broken. The patch fixes this bug by overriding the serirq_mode option in the devicetree.cb to set Continuous SIRQ mode Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 158801f118..3067ffe53c 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -62,6 +62,9 @@ chip soc/intel/skylake
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
+ # Set LPC Serial IRQ mode
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
register "PmConfigSlpS3MinAssert" = "0x02"