diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-04 21:33:39 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2015-01-06 01:51:42 +0100 |
| commit | 77757c22b9eede92234d07d65a23fdf4b970c8cf (patch) | |
| tree | 29949ed8cfac9c5c9b2cf4c8071c74690411d32d /src/mainboard/asrock | |
| parent | d76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 (diff) | |
| download | coreboot-77757c22b9eede92234d07d65a23fdf4b970c8cf.tar.xz | |
mainboard/*/romstage.c: Sanitize system header inclusions
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/939a785gmh/romstage.c | 12 | ||||
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/asrock/imb-a180/romstage.c | 8 |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 417f9a7845..16cc02b213 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -27,18 +27,18 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -52,7 +52,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 604c923fc2..aabdd74918 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,10 +31,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 1ba1104eb0..efeed35005 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> |