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| author | Felix Held <felix-coreboot@felixheld.de> | 2018-07-25 11:43:19 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-26 12:39:01 +0000 |
| commit | de690a30a4c5c9f22dec0c606a82cf10216ecaf7 (patch) | |
| tree | 1714e41e0318527bdccf4f0b87b76958faf891d9 /src/mainboard/asrock | |
| parent | 4c2f26c9fc37c65b23bf10fbe6d8389e50d04483 (diff) | |
| download | coreboot-de690a30a4c5c9f22dec0c606a82cf10216ecaf7.tar.xz | |
asrock/g41c-gs: make serial console setup depend on selected super IO
The used super IO is selected in Kconfig depending on the board variant, so use
the selected super IO instead of the board variant directly.
Change-Id: I8421e7c9b1f9ca875c9291f4105c3c20726adfd0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index e1f4152a4d..49a44d9685 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -47,7 +47,7 @@ static void mb_lpc_setup(void) setup_pch_gpios(&mainboard_gpio_map); /* Set GPIOs on superio, enable UART */ - if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) { + if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); @@ -57,7 +57,7 @@ static void mb_lpc_setup(void) nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); - } else { /* BOARD_ASROCK_G41C_GS */ + } else { winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); } /* IRQ routing */ |