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authorefdesign98 <efdesign98@gmail.com>2011-06-20 17:38:49 -0700
committerMarc Jones <marcj303@gmail.com>2011-06-22 01:27:46 +0200
commit05a89ab922473f375820a3bd68691bb085c62448 (patch)
tree22510d53ab35d80987cb17f2a11ce08039db49a5 /src/mainboard/asrock
parentee39ea7e7edf9699f1bae1b2708ad6816f054817 (diff)
downloadcoreboot-05a89ab922473f375820a3bd68691bb085c62448.tar.xz
Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/Kconfig8
-rw-r--r--src/mainboard/asrock/e350m1/devicetree.cb18
2 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index fdcc3c9ab3..e6153c01f2 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -22,10 +22,10 @@ if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_X86
- select CPU_AMD_AGESA_WRAPPER_FAMILY14
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14_ROOT_COMPLEX
- select NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14
- select SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+ select CPU_AMD_AGESA_FAMILY14
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+ select NORTHBRIDGE_AMD_AGESA_FAMILY14
+ select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 43607ebb02..5983ed2148 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -16,17 +16,17 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-chip northbridge/amd/agesa_wrapper/family14/root_complex
+chip northbridge/amd/agesa/family14/root_complex
device lapic_cluster 0 on
- chip cpu/amd/agesa_wrapper/family14
+ chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device pci_domain 0 on
subsystemid 0x1022 0x1510 inherit
- chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
- chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex
+ chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal Multimedia
@@ -35,9 +35,9 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
- end # agesa_wrapper northbridge
+ end # agesa northbridge
- chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus
+ chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
@@ -113,7 +113,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
register "gpp_configuration" = "4"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
- end #southbridge/amd/cimx_wrapper/sb800
+ end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.0 on end
@@ -125,7 +125,7 @@ chip northbridge/amd/agesa_wrapper/family14/root_complex
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
- end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex
+ end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #pci_domain
-end #northbridge/amd/agesa_wrapper/family14/root_complex
+end #northbridge/amd/agesa/family14/root_complex