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authorAamir Bohra <aamir.bohra@intel.com>2019-09-10 08:39:14 +0530
committerFurquan Shaikh <furquan@google.com>2019-09-12 06:19:53 +0000
commit87bb5f5e7a4476a2e9a70cc8d234fa0b479f1e26 (patch)
tree975b13fd344aa8af8f505fc6a7970e0c44a5b43f /src/mainboard/asrock
parent0e3c245c6cf4b8fe415c3309098cd51795d90fcf (diff)
downloadcoreboot-87bb5f5e7a4476a2e9a70cc8d234fa0b479f1e26.tar.xz
soc/intel/cannonlake: Add config for sata devslp pad reset configuration
CML FSP now provides a provision to configure the SATA devslp GPIO pad reset configuration. This config would help set the the required pad reset configuration. BUG=b:133000685 Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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