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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-10-27 15:07:00 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-10-31 10:34:33 +0000
commit9a100b5c1df00b4b4570f914412068e3d86343f4 (patch)
tree272f4d6e694e703c4543967f8d3fc3b34b399b40 /src/mainboard/asrock
parentdb8f9229b1a17a5084c828ff8b078cec45f6ac99 (diff)
downloadcoreboot-9a100b5c1df00b4b4570f914412068e3d86343f4.tar.xz
mb/asrock/h110m: configure SuperIO Deep Sleep
Change-Id: I10766ffda67bdc830ab01436ebd0578c79f1ec70 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index acb2a9e629..b2a2d72df2 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -415,10 +415,10 @@ chip soc/intel/skylake
device pnp 2e.14 off end # SVID, Port 80 UART
device pnp 2e.16 off end # DS5
device pnp 2e.116 off end # DS3
- device pnp 2e.316 off end # PCHDSW
+ device pnp 2e.316 on end # PCHDSW
device pnp 2e.416 off end # DSWWOPT
- device pnp 2e.516 off end # DS3OPT
- device pnp 2e.616 off end # DSDSS
+ device pnp 2e.516 on end # DS3OPT
+ device pnp 2e.616 on end # DSDSS
device pnp 2e.716 off end # DSPU
end # superio/nuvoton/nct6791d
chip drivers/pc80/tpm