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authorIdwer Vollering <vidwer@gmail.com>2020-01-05 01:44:25 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-09 16:03:07 +0000
commitc2ce370f30b60daf60e23182cf01eb898d35fbbd (patch)
tree7b4fc0f6682a74264c617a26010a8bb1be215a4c /src/mainboard/asrock
parent7c0711092371a7e92c7b37d252ac4a74992dac87 (diff)
downloadcoreboot-c2ce370f30b60daf60e23182cf01eb898d35fbbd.tar.xz
src/mainboard: remove MMIO macros
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/imb-a180/bootblock.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/src/mainboard/asrock/imb-a180/bootblock.c b/src/mainboard/asrock/imb-a180/bootblock.c
index f6bd5c40de..eb5641ff5e 100644
--- a/src/mainboard/asrock/imb-a180/bootblock.c
+++ b/src/mainboard/asrock/imb-a180/bootblock.c
@@ -21,23 +21,20 @@
void bootblock_mainboard_early_init(void)
{
- volatile u32 *addr32;
- u32 t32;
+ u32 reg32;
/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
pm_write8(0xea, 0x1);
/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
- addr32 = (u32 *)0xfed80e28;
- t32 = *addr32;
- t32 &= 0xfff8ffff;
- *addr32 = t32;
+ reg32 = misc_read32(0x28);
+ reg32 &= 0xfff8ffff;
+ misc_write32(0x28, reg32);
/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
- addr32 = (u32 *)0xfed80e40;
- t32 = *addr32;
- t32 &= 0xffffbffb;
- *addr32 = t32;
+ reg32 = misc_read32(0x40);
+ reg32 &= 0xffffbffb;
+ misc_write32(0x40, reg32);
/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);