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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 14:46:47 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 09:58:33 +0000 |
| commit | 45f448f4a4e09b270d964c98d3aced2e73d9d6bc (patch) | |
| tree | d217f38c8a28fbf1c449f17f243b73a7f23db6dd /src/mainboard/asrock | |
| parent | c05c2b3fb25ca42a75ecc987178c298f7fe0ead5 (diff) | |
| download | coreboot-45f448f4a4e09b270d964c98d3aced2e73d9d6bc.tar.xz | |
haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/b85m_pro4/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index c99bb6f422..975ad39f85 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> +#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -21,9 +21,9 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -70,5 +70,5 @@ void mainboard_romstage_entry(void) }, }; - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 5ce0145199..b4d44291c9 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> +#include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -21,9 +21,9 @@ void mainboard_config_rcba(void) RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); } -void mainboard_romstage_entry(void) +void mainboard_fill_pei_data(struct pei_data *pei_data) { - struct pei_data pei_data = { + struct pei_data mainboard_pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, @@ -70,5 +70,5 @@ void mainboard_romstage_entry(void) }, }; - romstage_common(&pei_data); + *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ } |