diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-25 14:20:57 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-12-20 07:18:00 +0100 |
| commit | 48518f0d60478a9277cd50158fbf28f56ae97532 (patch) | |
| tree | a24f0ed3cba3a646555370c7714fa27fb8441b5f /src/mainboard/asrock | |
| parent | 5b7e54306a2d28297baf0db78c30a34627a95038 (diff) | |
| download | coreboot-48518f0d60478a9277cd50158fbf28f56ae97532.tar.xz | |
AGESA: Add amd_initcpuio() and amd_initmmio()
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/asrock/imb-a180/romstage.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index ea59a8d805..911e821664 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); - agesawrapper_amdinitmmio(); + amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 3d1458bed1..1ba1104eb0 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -55,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); - agesawrapper_amdinitmmio(); + amd_initmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); agesawrapper_amdinitresume(); - agesawrapper_amdinitcpuio(); + amd_initcpuio(); agesawrapper_amds3laterestore(); post_code(0x61); |