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authorAngel Pons <th3fanbus@gmail.com>2020-05-21 00:58:33 +0200
committerNico Huber <nico.h@gmx.de>2020-05-26 11:45:24 +0000
commit41b820cbd66da001b02a426a7b5cf1b7f011702a (patch)
tree72db6eebdf34554a5d219c17349d4148fca4294e /src/mainboard/asrock
parent0c983df7caa041f86f28938ccae31ce2d45803e5 (diff)
downloadcoreboot-41b820cbd66da001b02a426a7b5cf1b7f011702a.tar.xz
AGESA f14: Factor out default MTRR settings
All AGESA f14 boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Id980e4671e51fe800188f0a84768a307c8965886 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/buildOpts.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c
index 5583a8b118..1e2ebb07f1 100644
--- a/src/mainboard/asrock/e350m1/buildOpts.c
+++ b/src/mainboard/asrock/e350m1/buildOpts.c
@@ -62,23 +62,6 @@
* needed by the system.
*/
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
- { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
- { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
- { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
- { CPU_LIST_TERMINAL }
-};
-
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -108,7 +91,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
-#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
//#define BLDCFG_STARTING_BUSNUM 0
//#define BLDCFG_MAXIMUM_BUSNUM 0xf8