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authorStefan Reinauer <stefan.reinauer@coreboot.org>2011-04-20 20:54:07 +0000
committerStefan Reinauer <stepan@openbios.org>2011-04-20 20:54:07 +0000
commit42fa7fe28b60b448f501e99ee285a0af12c86d34 (patch)
tree247586f11a5be9dcbea2cbafaede92df058ac14b /src/mainboard/asrock
parentd8129f92c0cbd6a561195c1628ba3f9f98eccd50 (diff)
downloadcoreboot-42fa7fe28b60b448f501e99ee285a0af12c86d34.tar.xz
run uart_init() from console_init, just like the other console initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/939a785gmh/romstage.c1
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 25822d9e56..b0ae24794f 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -158,7 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sio_init();
w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- uart_init();
console_init();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index b48a58af6b..d63fbe81cb 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -53,7 +53,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x31);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- uart_init();
console_init();
}
//reg8 = pmio_read(0x24);