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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-05-29 14:29:45 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-08-20 15:18:10 +0000 |
| commit | 8216b46d7b9b88be4e31660362c4b9077670fd33 (patch) | |
| tree | 95b46818db052de8fa5224ff2919b2e16ed7797f /src/mainboard/asrock | |
| parent | ed316bc39cfb1f6dffcc76a245580b43ad5d0225 (diff) | |
| download | coreboot-8216b46d7b9b88be4e31660362c4b9077670fd33.tar.xz | |
mb/{asrock,intel,purism}: Copy channel arrays separately
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 136538{8,9}, 140134{1,4}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33135
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/h110m/romstage.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 4961a792ad..efbc650bf3 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -20,7 +20,7 @@ #define RCOMP_TARGET_PARAMS 0x5 -static void mainboard_fill_dq_map_data(void *dq_map_ptr) +static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -28,16 +28,18 @@ static void mainboard_fill_dq_map_data(void *dq_map_ptr) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -64,8 +66,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); |