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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/asrock
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl8
-rw-r--r--src/mainboard/asrock/g41c-gs/romstage.c2
-rw-r--r--src/mainboard/asrock/imb-a180/OemCustomize.c2
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
index 09d961d2b4..96870997f5 100644
--- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
@@ -18,7 +18,7 @@
* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
*/
-#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)
+#if CONFIG(BOARD_ASROCK_G41M_VS3_R2_0)
If (PICM) {
Return (Package() {
/* PCI1 SLOT 1 */
@@ -53,9 +53,9 @@ If (PICM) {
})
}
#else
-/* IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) \
- || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) \
- || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) */
+/* CONFIG(BOARD_ASROCK_G41C_GS_R2_0) \
+ || CONFIG(BOARD_ASROCK_G41C_GS) \
+ || CONFIG(BOARD_ASROCK_G41M_GS) */
If (PICM) {
Return (Package() {
/* PCI1 SLOT 1 */
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 8474d189a3..8cf34879dd 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -44,7 +44,7 @@ static void mb_lpc_setup(void)
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
- if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) {
+ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);
diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c
index 3b1c903b3a..eaa27b7957 100644
--- a/src/mainboard/asrock/imb-a180/OemCustomize.c
+++ b/src/mainboard/asrock/imb-a180/OemCustomize.c
@@ -102,7 +102,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}