diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-02-07 09:00:47 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-08 11:00:01 +0000 |
| commit | 8c905a82f5d07ae7936114d392ec897756c0df9d (patch) | |
| tree | 51da94b62ccb1acb79e74ea71e7a7201b6ea91a2 /src/mainboard/asrock | |
| parent | d5c458f98ad71f66815f637c5cb6305adc133b27 (diff) | |
| download | coreboot-8c905a82f5d07ae7936114d392ec897756c0df9d.tar.xz | |
mb/{asrock,intel,kontron}: Include missing <arch/io.h>
Also includes lines sorted
Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 0605ef1245..ab6b1d88ae 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -15,17 +15,18 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/x4x/x4x.h> -#include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/bist.h> +#include <northbridge/intel/x4x/iomap.h> +#include <northbridge/intel/x4x/x4x.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> -#include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <northbridge/intel/x4x/iomap.h> +#include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) |