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authorMarshall Buschman <mbuschman@lucidmachines.com>2011-06-04 15:44:31 +0000
committerPeter Stuge <peter@stuge.se>2011-06-04 15:44:31 +0000
commitb3ee0d6bd6df18b61779f64c8b0abf19b1dce018 (patch)
treefb574b610b964d3e95a9806e2edde42e4ef336f3 /src/mainboard/asrock
parent69e1bfcf341713be9cafa3565a0329a902cfb4f1 (diff)
downloadcoreboot-b3ee0d6bd6df18b61779f64c8b0abf19b1dce018.tar.xz
Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time. Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/romstage.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index d63fbe81cb..d761d73555 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,6 +47,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
u32 val;
u8 reg8;
+ // early enable of SPI 33 MHz fast mode read
+ if (boot_cpu())
+ {
+ volatile u32 *spiBase = (void *) 0xa0000000;
+ u32 save;
+ __outdword (0xcf8, 0x8000a3a0);
+ save = __indword (0xcfc);
+ __outdword (0xcfc, (u32) spiBase | 2); // set temp MMIO base
+ spiBase [3] = (spiBase [3] & ~(3 << 14)) | (1 << 14);
+ spiBase [0] |= 1 << 18; // fast read enable
+ __outdword (0xcfc, save); // clear temp base
+ }
+
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();