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| author | Marc Jones <marc.jones@amd.com> | 2008-09-23 22:19:27 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-09-23 22:19:27 +0000 |
| commit | 3aca4b5734e13dc5a40d238421be8c0f072ee552 (patch) | |
| tree | 6f1b98f3b90dca3aebda680f02f11c5c4feb435e /src/mainboard/asus/a8n_e | |
| parent | 0f4282b538213c17913821bc8e84877074838edf (diff) | |
| download | coreboot-3aca4b5734e13dc5a40d238421be8c0f072ee552.tar.xz | |
The AMD dbm690t mainboard uses the it8712f SIO with the
default 48MHz clock input. The Asus a8n_e uses the it8712f
with a 24MHz clock input. The it8712f early init code was
setting a 24MHz input clock(to support the a8n_e).
Since 48Mhz is the default I added a function to set 24MHz
input clock to the a8n_e.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/a8n_e')
| -rw-r--r-- | src/mainboard/asus/a8n_e/cache_as_ram_auto.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c index 41af6ca528..5f8e93ba4e 100644 --- a/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -221,6 +221,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); } + it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); |