W83627DHG/W83627EHG fixups for virtual LDNs.

W83627DHG:

 - Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
   that don't have their "enable" bit in bit 0 of the 0x30 register).

 - Fix various I/O masks in the pnp_dev_info[] array as per
   datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.

W83627EHG:

 - Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
   mostly implemented already, though).

 - Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.

Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.

include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.

asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.

ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 6 insertions, 6 deletions

diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
index b99ebfeb26..cd803929c8 100644
--- a/src/mainboard/asus/a8v-e_se/devicetree.cb
+++ b/src/mainboard/asus/a8v-e_se/devicetree.cb
@@ -49,9 +49,9 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
                 io 0x60 = 0x2f8
                 irq 0x70 = 3
               end
-              device pnp 2e.5 off		# PS/2 keyboard (off)
+              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
               end
-              device pnp 2e.106 off		# Serial flash
+              device pnp 2e.106 off		# Serial flash interface (SFI)
                 io 0x60 = 0x100
               end
               device pnp 2e.007 off		# GPIO 1
@@ -65,15 +65,15 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
               end
               device pnp 2e.307 off		# GPIO 6
               end
-              device pnp 2e.8 off		# WDTO_PLED
+              device pnp 2e.8 off		# WDTO#, PLED
               end
-              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              device pnp 2e.009 on		# GPIO 2
               end
               device pnp 2e.109 off		# GPIO 3
               end
               device pnp 2e.209 off		# GPIO 4
               end
-              device pnp 2e.309 on		# GPIO5
+              device pnp 2e.309 on		# GPIO 5
               end
               device pnp 2e.a off		# ACPI
               end
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 1167832c6a..1f3c088858 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -49,7 +49,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
+#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }