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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/asus/a8v-e_se
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
downloadcoreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/a8v-e_se')
-rw-r--r--src/mainboard/asus/a8v-e_se/Config.lb28
-rw-r--r--src/mainboard/asus/a8v-e_se/Options.lb188
-rw-r--r--src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c10
3 files changed, 113 insertions, 113 deletions
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
index a53b262d16..242c104eac 100644
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ b/src/mainboard/asus/a8v-e_se/Config.lb
@@ -20,42 +20,42 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
default CONFIG_ROM_PAYLOAD = 1
arch i386 end
driver mainboard.o
-if HAVE_ACPI_TABLES
+if CONFIG_HAVE_ACPI_TABLES
object acpi_tables.o
makerule dsdt.c
- depends "$(MAINBOARD)/dsdt.asl"
- action "iasl -p $(CURDIR)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+ depends "$(CONFIG_MAINBOARD)/dsdt.asl"
+ action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
action "mv dsdt.hex dsdt.c"
end
object ./dsdt.o
end
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
mainboardinit southbridge/via/k8t890/romstrap.inc
@@ -71,7 +71,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/amd/car/cache_as_ram.lds
end
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -81,7 +81,7 @@ end
mainboardinit cpu/amd/car/cache_as_ram.inc
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
index a471b418b2..75c404dd92 100644
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ b/src/mainboard/asus/a8v-e_se/Options.lb
@@ -17,156 +17,156 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-# uses USE_OPTION_TABLE
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+# uses CONFIG_USE_OPTION_TABLE
# uses CONFIG_LB_MEM_TOPK
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses K8_HT_FREQ_1G_SUPPORT
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
# bx_b005+
-uses SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_USE_PRINTK_IN_CAR
-default ROM_SIZE = 512 * 1024
-default FALLBACK_SIZE = 256 * 1024
-default HAVE_FALLBACK_BOOT = 1
-default HAVE_HARD_RESET = 0
-default HAVE_PIRQ_TABLE = 0
-default IRQ_SLOT_COUNT = 11 # FIXME?
-default HAVE_MP_TABLE = 1
-default HAVE_OPTION_TABLE = 0 # FIXME
+default CONFIG_ROM_SIZE = 512 * 1024
+default CONFIG_FALLBACK_SIZE = 256 * 1024
+default CONFIG_HAVE_FALLBACK_BOOT = 1
+default CONFIG_HAVE_HARD_RESET = 0
+default CONFIG_HAVE_PIRQ_TABLE = 0
+default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME?
+default CONFIG_HAVE_MP_TABLE = 1
+default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME
# Move the default coreboot CMOS range off of AMD RTC registers.
-default LB_CKS_RANGE_START = 49
-default LB_CKS_RANGE_END = 122
-default LB_CKS_LOC = 123
+default CONFIG_LB_CKS_RANGE_START = 49
+default CONFIG_LB_CKS_RANGE_END = 122
+default CONFIG_LB_CKS_LOC = 123
default CONFIG_SMP = 1
default CONFIG_MAX_CPUS = 2
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
-default HAVE_ACPI_TABLES = 1
+default CONFIG_HAVE_ACPI_TABLES = 1
# 1G memory hole
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
# Opteron K8 1G HT support
-default K8_HT_FREQ_1G_SUPPORT = 1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
# HT Unit ID offset, default is 1, the typical one.
-default HT_CHAIN_UNITID_BASE = 0x0
+default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default HT_CHAIN_END_UNITID_BASE = 0x0
+# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
# Make the SB HT chain on bus 0, default is not (0).
# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
# bx_b005+ make the SB HT chain on bus 0.
-default SB_HT_CHAIN_ON_BUS0 = 1
+default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
# Only offset for SB chain?, default is yes(1).
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA.
-default USE_DCACHE_RAM = 1
-default DCACHE_RAM_BASE = 0xcc000
-default DCACHE_RAM_SIZE = 0x4000
-default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
+default CONFIG_USE_DCACHE_RAM = 1
+default CONFIG_DCACHE_RAM_BASE = 0xcc000
+default CONFIG_DCACHE_RAM_SIZE = 0x4000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
default CONFIG_USE_INIT = 0
-default ENABLE_APIC_EXT_ID = 0
-default APIC_ID_OFFSET = 0x10
-default LIFT_BSP_APIC_ID = 0
+default CONFIG_ENABLE_APIC_EXT_ID = 0
+default CONFIG_APIC_ID_OFFSET = 0x10
+default CONFIG_LIFT_BSP_APIC_ID = 0
default CONFIG_IOAPIC = 1
-default MAINBOARD_VENDOR = "ASUS"
-default MAINBOARD_PART_NUMBER = "A8V-E SE"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
-default ROM_IMAGE_SIZE = 64 * 1024
-default STACK_SIZE = 8 * 1024
-default HEAP_SIZE = 256 * 1024
+default CONFIG_MAINBOARD_VENDOR = "ASUS"
+default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
+default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
+default CONFIG_STACK_SIZE = 8 * 1024
+default CONFIG_HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
# default CONFIG_LB_MEM_TOPK = 2048
-default _RAMBASE = 0x00004000
-# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_RAMBASE = 0x00004000
+# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
+default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC = "gcc"
default CONFIG_GDB_STUB = 0
default CONFIG_USE_PRINTK_IN_CAR = 1
default CONFIG_CONSOLE_SERIAL8250 = 1
-default TTYS0_BAUD = 115200
-default TTYS0_BASE = 0x3f8
-default TTYS0_LCS = 0x3 # 8n1
-default DEFAULT_CONSOLE_LOGLEVEL = 8
-default MAXIMUM_CONSOLE_LOGLEVEL = 8
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
+default CONFIG_TTYS0_BAUD = 115200
+default CONFIG_TTYS0_BASE = 0x3f8
+default CONFIG_TTYS0_LCS = 0x3 # 8n1
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
#
# CBFS
#
diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
index 0a8ca60a8b..b76d011910 100644
--- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
+++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
@@ -178,7 +178,7 @@ void sio_init(void)
pnp_exit_ext_func_mode(GPIO_DEV);
}
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -187,7 +187,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned last_boot_normal_x = 1;
sio_init();
- w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();
@@ -232,7 +232,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -251,11 +251,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
- (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
char *p;
sio_init();
- w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
enable_rom_decode();