summaryrefslogtreecommitdiff
path: root/src/mainboard/asus/f2a85-m
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-03 12:36:09 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-09 05:23:55 +0000
commit657d68bddc030e38bc19eb4eef07f59b5e5258e4 (patch)
tree90d064a1e09721ae2e9279117ecb71f8ede854eb /src/mainboard/asus/f2a85-m
parentdafc78bb8d6bda8bddb029168491365b333ce529 (diff)
downloadcoreboot-657d68bddc030e38bc19eb4eef07f59b5e5258e4.tar.xz
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/asus/f2a85-m')
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index d5acdb55e3..8a48e0080c 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -68,11 +68,6 @@ void board_BeforeAgesa(struct sysinfo *cb)
u8 byte;
pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE))
- hudson_pci_port80();
- else if (CONFIG(POST_DEVICE_LPC))
- hudson_lpc_port80();
-
/* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);