mainboard/asus: Move F2A85-M_LE variant to F2A85-M.

Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.

Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

6 files changed, 207 insertions, 30 deletions

diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
index 98bb06781e..b1686d0723 100644
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
@@ -42,6 +42,7 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
  * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
  * the vendor BIOS.
  */
+#if !IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
 const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
 	{0x11, 0x99430140},
 	{0x12, 0x411111f0},
@@ -59,6 +60,25 @@ const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
 	{0x1f, 0x411111f0},
 	{0xff, 0xffffffff}
 };
+#else
+const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
+	{0x11, 0x99430140},
+	{0x12, 0x411111f0},
+	{0x14, 0x01014010},
+	{0x15, 0x411111f0},
+	{0x16, 0x411111f0},
+	{0x17, 0x411111f0},
+	{0x18, 0x01a19850},
+	{0x19, 0x02a19c60},
+	{0x1a, 0x0181305f},
+	{0x1b, 0x02214c20},
+	{0x1c, 0x411111f0},
+	{0x1d, 0x4004c601},
+	{0x1e, 0x01456130},
+	{0x1f, 0x411111f0},
+	{0xff, 0xffffffff}
+};
+#endif
 
 static const CODEC_TBL_LIST CodecTableList[] =
 {
diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index 03c9c28bd3..f3b2d7d3aa 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -14,7 +14,7 @@
 # GNU General Public License for more details.
 #
 
-if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
+if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -25,7 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
-	select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M
+	select SUPERIO_ITE_IT8728F if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_LE
 	select SUPERIO_NUVOTON_NCT6779D if BOARD_ASUS_F2A85_M_PRO
 	select BOARD_ROMSIZE_KB_8192
 	select GFXUMA
@@ -62,6 +62,7 @@ config MAINBOARD_DIR
 config MAINBOARD_PART_NUMBER
 	string
 	default "F2A85-M" if BOARD_ASUS_F2A85_M
+	default "F2A85-M_LE" if BOARD_ASUS_F2A85_M_LE
 	default "F2A85-M_PRO" if BOARD_ASUS_F2A85_M_PRO
 
 config HW_MEM_HOLE_SIZEK
@@ -92,6 +93,8 @@ config ONBOARD_VGA_IS_PRIMARY
 	bool
 	default y
 
+if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
+
 config VGA_BIOS_ID
 	string
 	default "1002,9993"
@@ -104,9 +107,24 @@ config POST_IO
 	bool
 	default n
 
+endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
+
+if BOARD_ASUS_F2A85_M_LE
+
+config VGA_BIOS_ID
+	string
+	default "1002,9901"
+
+config VGA_BIOS_FILE
+	string
+	default "pci1002,9901.rom"
+
+endif
+
 config DEVICETREE
 	string
 	default "devicetree_f2a85-m_pro.cb" if BOARD_ASUS_F2A85_M_PRO
 	default "devicetree_f2a85-m.cb" if BOARD_ASUS_F2A85_M
+	default "devicetree_f2a85-m_le.cb" if BOARD_ASUS_F2A85_M_LE
 
-endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO
+endif # BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
diff --git a/src/mainboard/asus/f2a85-m/Kconfig.name b/src/mainboard/asus/f2a85-m/Kconfig.name
index a8aa273954..8a3d7ef1d1 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig.name
+++ b/src/mainboard/asus/f2a85-m/Kconfig.name
@@ -3,3 +3,6 @@ config BOARD_ASUS_F2A85_M
 
 config BOARD_ASUS_F2A85_M_PRO
 	bool "F2A85-M PRO"
+
+config BOARD_ASUS_F2A85_M_LE
+	bool "F2A85-M LE"
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index d5452074f4..fa99d70643 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -205,7 +205,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
  *----------------------------------------------------------------------------------------
  */
 
-#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M)
+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
 /*
  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@@ -225,7 +225,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
   */
   PSO_END
 };
-#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
+#elif IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
 /*
  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@@ -234,7 +234,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  */
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 /*
   TODO: is this OK for DDR3 socket FM2?
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
new file mode 100644
index 0000000000..d83f466116
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb
@@ -0,0 +1,132 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family15tn
+			device lapic 10 on end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+				device pci 0.0 on  end # Root Complex
+				device pci 0.2 on  end # IOMMU
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
+				device pci 1.1 on  end # Internal Multimedia
+				device pci 2.0 on  end # PCIE SLOT0 x16 blue
+				device pci 3.0 off end # unused?
+				device pci 4.0 on  end # PCIE 4x black
+				device pci 5.0 off end # unused?
+				device pci 6.0 off end # unused?
+				device pci 7.0 off end # LAN
+				device pci 8.0 off end # NB/SB Link P2P bridge
+			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 on  end # XHCI HC0
+				device pci 10.1 on  end # XHCI HC1
+				device pci 11.0 on  end # SATA
+				device pci 12.0 on  end # USB
+				device pci 12.2 on  end # USB
+				device pci 13.0 on  end # USB
+				device pci 13.2 on  end # USB
+				device pci 14.0 on      # SMBUS
+					chip drivers/generic/generic #dimm 0
+						device i2c 50 on end # 7-bit SPD address
+					end
+					chip drivers/generic/generic #dimm 1
+						device i2c 51 on end # 7-bit SPD address
+					end
+				end # SM
+				device pci 14.1 off end # IDE	0x439c
+				device pci 14.2 on  end # HDA	0x4383
+				device pci 14.3 on      # LPC	0x439d
+					chip superio/ite/it8728f
+						register hwm_ctl_register = "0xc0"
+						register hwm_main_ctl_register = "0x33"
+						register hwm_adc_temp_chan_en_reg = "0x38"
+						register hwm_fan1_ctl_pwm = "0x00"
+						register hwm_fan2_ctl_pwm = "0x00"
+						register hwm_fan3_ctl_pwm = "0x00"
+
+						device pnp 2e.0 off #  Floppy
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
+						end
+						device pnp 2e.1 on #  Com1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off #  Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 off #  Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp 2e.4 on #  Env Controller
+							io 0x60 = 0x290
+							io 0x62 = 0x220
+							irq 0x70 = 0
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 off #  Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on #  GPIO
+							io 0x60 = 0x228 #SMI
+							io 0x62 = 0x300 #Simple I/O
+							io 0x64 = 0x238 #Phony resource IT8603E does not have it
+							irq 0x70 = 0
+						end
+						device pnp 2e.a off end #  CIR
+					end	#superio/ite/it8728f
+				end	#device pci 14.3 # LPC
+				device pci 14.4 on  end # PCI 0x4384
+				device pci 14.5 on  end # USB 2
+				device pci 14.6 off end # Gec
+				device pci 14.7 off end # SD
+				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+				device pci 15.1 on end # PCIe 1 onboard gigabit
+				device pci 15.2 off end # unused
+				device pci 15.3 off end # unused
+			end	#chip southbridge/amd/agesa/hudson
+
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+
+		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+	end	#domain
+end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index d66c7d52bd..77024a01c3 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -35,26 +35,16 @@
 #include <southbridge/amd/agesa/hudson/smbus.h>
 #include <stdint.h>
 #include <string.h>
-#if CONFIG_BOARD_ASUS_F2A85_M
+
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8728f/it8728f.h>
-#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
-#endif /* CONFIG_BOARD_ASUS_F2A85_M */
-
 
 #define MMIO_NON_POSTED_START 0xfed00000
 #define MMIO_NON_POSTED_END   0xfedfffff
 #define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
 
-#if CONFIG_BOARD_ASUS_F2A85_M
-#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
-#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
-#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
-#endif /* CONFIG_BOARD_ASUS_F2A85_M */
-
 static void sbxxx_enable_48mhzout(void)
 {
 	/* most likely programming to 48MHz out signal */
@@ -69,6 +59,23 @@ static void sbxxx_enable_48mhzout(void)
 	SB_MMIO_MISC32(0x40) = reg32;
 }
 
+static void superio_init_m(void)
+{
+	pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+	pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+	ite_kill_watchdog(gpio);
+	ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+	ite_enable_3vsbsw(gpio);
+}
+
+static void superio_init_m_pro(void)
+{
+	pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
+
+	nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
@@ -78,12 +85,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* Must come first to enable PCI MMCONF. */
 	amd_initmmio();
 
-#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
-	hudson_pci_port80();
-#endif
-#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
-	hudson_lpc_port80();
-#endif
+	if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+		hudson_pci_port80();
+	else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+		hudson_lpc_port80();
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 
@@ -106,13 +111,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		/* enable SIO clock */
 		sbxxx_enable_48mhzout();
-#if CONFIG_BOARD_ASUS_F2A85_M
-		ite_kill_watchdog(GPIO_DEV);
-		ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-		ite_enable_3vsbsw(GPIO_DEV);
-#elif CONFIG_BOARD_ASUS_F2A85_M_PRO
-		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-#endif
+
+		if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
+			superio_init_m_pro();
+		else
+			superio_init_m();
+
 		console_init();
 
 		/* turn on secondary smbus at b20 */