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author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 14:30:50 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-20 17:47:40 +0000 |
commit | 945fe766a1c4cc939fbc5da03259d4d8c413bfa5 (patch) | |
tree | a2a33460ce90a6fa32ad3bdffc84ccb12ffe21a0 /src/mainboard/asus/h61-series/devicetree.cb | |
parent | 348639c4603852f70c161aa58b986e1a7e37962e (diff) | |
download | coreboot-945fe766a1c4cc939fbc5da03259d4d8c413bfa5.tar.xz |
mb/asus/p8h61-m_lx3_r2_0: Extract overridetree
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0
remains identical when not adding the .config file in it.
Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54387
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/h61-series/devicetree.cb')
-rw-r--r-- | src/mainboard/asus/h61-series/devicetree.cb | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb new file mode 100644 index 0000000000..07c0a866c3 --- /dev/null +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -0,0 +1,50 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax + register "acpi_c1" = "1" + register "acpi_c2" = "3" + register "acpi_c3" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0 on + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 02.0 on end # iGPU + + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 16.2 off end # ME IDE-R + device pci 16.3 off end # ME KT + device pci 19.0 off end # Intel GbE + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 off end # RP #6 + device pci 1c.6 off end # RP #7 + device pci 1c.7 off end # RP #8 + + device pci 1d.0 on end # EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + device pci 1f.6 off end # Thermal + end + end +end |