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| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 13:22:57 +0200 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2021-05-20 17:10:01 +0000 |
| commit | ed1e25de525fe2649bf5af2b448f7b37e34c54f6 (patch) | |
| tree | aa3f9f493ba748831c93fafd676388087f3c3d57 /src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout | |
| parent | 9d8a4558e30845ff9ae421c551b4fa51dcfeec93 (diff) | |
| download | coreboot-ed1e25de525fe2649bf5af2b448f7b37e34c54f6.tar.xz | |
mb/asus/p8h61-m_lx: Transform into variant setup
Handle some differences in the DSDT code using preprocessor.
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX
remains identical when not adding the .config file in it.
Change-Id: I2a02f32dfd9fa9c1adce3baf0d279ea19db5883f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout')
| -rw-r--r-- | src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout new file mode 100644 index 0000000000..782a1b8c10 --- /dev/null +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/cmos.layout @@ -0,0 +1,73 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +412 3 e 7 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +6 0 AHCI +6 1 Compatible + +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 |