mb/asus/p8h61-m_lx: Switch to overridetree setup

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX
remains identical when not adding the .config file in it.

Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 85 insertions, 0 deletions

diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb
new file mode 100644
index 0000000000..aa9f8c81b9
--- /dev/null
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb
@@ -0,0 +1,85 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1043 0x844d inherit
+		chip southbridge/intel/bd82x6x
+			register "gen1_dec" = "0x00000295" # Super I/O HWM
+
+			device pci 1b.0 on      # HD audio controller
+				subsystemid 0x1043 0x8445
+			end
+			device pci 1c.0 on  end # PCIe 1x slot (PCIEX1_1)
+			device pci 1c.1 on  end # PCIe 1x slot (PCIEX1_2)
+			device pci 1c.2 on      # Realtek Gigabit Ethernet
+				subsystemid 0x1043 0x8432
+				chip drivers/net
+					register "customized_leds" = "0x00f6"
+					device pci 00.0 on end
+				end
+			end
+			device pci 1c.3 off end # Unused PCIe port
+			device pci 1c.4 on  end # PCIe 1x slot (PCIEX1_3)
+			device pci 1c.5 off end # Unused PCIe port
+			device pci 1c.6 off end # Unused PCIe port
+			device pci 1c.7 off end # Unused PCIe port
+
+			device pci 1f.0 on      # LPC bridge
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0   off end # Floppy
+					device pnp 2e.1   on      # Parallel
+						io  0x60 = 0x0378
+						irq 0x70 = 7
+						drq 0x74 = 4      # No DMA
+						irq 0xf0 = 0x3c   # Printer mode
+					end
+					device pnp 2e.2   on      # UART A
+						io  0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3   off end # UART B, IR
+					device pnp 2e.5   on      # PS/2 KBC
+						io  0x60 = 0x0060
+						io  0x62 = 0x0064
+						irq 0x70 = 1      # Keyboard
+						irq 0x72 = 12     # Mouse
+					end
+					device pnp 2e.6   off end # CIR
+					device pnp 2e.7   off end # GPIO8
+					device pnp 2e.107 off end # GPIO9
+					device pnp 2e.8   off end # WDT
+					device pnp 2e.108 off end # GPIO0
+					device pnp 2e.208 off end # GPIOA
+					device pnp 2e.308 off end # GPIO base
+					device pnp 2e.109 off end # GPIO1
+					device pnp 2e.209 off end # GPIO2
+					device pnp 2e.309 off end # GPIO3
+					device pnp 2e.409 off end # GPIO4
+					device pnp 2e.509 off end # GPIO5
+					device pnp 2e.609 off end # GPIO6
+					device pnp 2e.709 off end # GPIO7
+					device pnp 2e.a   on      # ACPI
+						# Power RAM in S3.
+						irq 0xe4 = 0x10
+					end
+					device pnp 2e.b   on      # HWM, LED
+						io  0x60 = 0x0290
+						io  0x62 = 0x0200
+
+						# Global registers to select
+						# HWM/LED functions instead of
+						# floppy functions.
+						irq 0x1c = 0x03
+						irq 0x24 = 0x24
+					end
+					device pnp 2e.d   off end # VID
+					device pnp 2e.e   off end # CIR wake-up
+					device pnp 2e.f   off end # GPIO PP/OD
+					device pnp 2e.14  off end # SVID
+					device pnp 2e.16  off end # Deep sleep
+					device pnp 2e.17  off end # GPIOA
+				end
+			end
+		end
+	end
+end