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authorAngel Pons <th3fanbus@gmail.com>2021-05-17 14:04:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-05-20 17:46:17 +0000
commit3ec960a482b45ee88a1b86be90bf71b9b5e0c4ac (patch)
tree95534c39181897a3a22ade029443855f85c78744 /src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
parent270ce521de9b597337fe7e544eeb78a1a0ecfa47 (diff)
downloadcoreboot-3ec960a482b45ee88a1b86be90bf71b9b5e0c4ac.tar.xz
mb/asus/h61-series: Consolidate devicetree SATA options
The H61 PCH only supports 4 SATA ports, and does not support Gen3. Change-Id: I3e060ca6904fd6c773c322988a17bbca28333a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb')
-rw-r--r--src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
index 9ad86610cd..62dbb378c2 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291"
- register "sata_port_map" = "0x3f"
+ register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"